crypto/hisilicon/qm.c

456 	return readl(qm->io_base + QM_ABNORMAL_INT_STATUS);
535 	return readl_relaxed_poll_timeout(qm->io_base + QM_MB_CMD_SEND_BASE,
544 	void __iomem *fun_base = qm->io_base + QM_MB_CMD_SEND_BASE;
587 	val = readl(qm->io_base + QM_MB_CMD_SEND_BASE);
681 	writeq(doorbell, qm->io_base + QM_DOORBELL_BASE_V1);
686 	void __iomem *io_base = qm->io_base;
691 		io_base = qm->db_io_base + (u64)qn * qm->db_interval +
694 		io_base += QM_DOORBELL_EQ_AEQ_BASE_V2;
701 	writeq(doorbell, io_base);
720 	val = readl(qm->io_base + QM_PM_CTRL);
722 	writel(val, qm->io_base +  QM_PM_CTRL);
729 	writel(0x1, qm->io_base + QM_MEM_START_INIT);
730 	return readl_relaxed_poll_timeout(qm->io_base + QM_MEM_INIT_DONE, val,
759 		val = readl(qm->io_base + info_table[index].offset);
957 	val = readl(qm->io_base + QM_IFC_INT_STATUS);
1104 	writel(page_type, qm->io_base + QM_PAGE_SIZE);
1216 	writel(lower_32_bits(tmp), qm->io_base + QM_VFT_CFG_DATA_L);
1217 	writel(upper_32_bits(tmp), qm->io_base + QM_VFT_CFG_DATA_H);
1230 	ret = readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
1236 	writel(0x0, qm->io_base + QM_VFT_CFG_OP_WR);
1237 	writel(type, qm->io_base + QM_VFT_CFG_TYPE);
1241 	writel(fun_num, qm->io_base + QM_VFT_CFG);
1245 	writel(0x0, qm->io_base + QM_VFT_CFG_RDY);
1246 	writel(0x1, qm->io_base + QM_VFT_CFG_OP_ENABLE);
1248 	return readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
1263 	writel(qm->type_rate, qm->io_base + QM_SHAPER_CFG);
1310 	sqc_vft = readl(qm->io_base + QM_MB_CMD_DATA_ADDR_L) |
1311 		  ((u64)readl(qm->io_base + QM_MB_CMD_DATA_ADDR_H) << 32);
1321 	writel(QM_ABNORMAL_INT_MASK_VALUE, qm->io_base + QM_ABNORMAL_INT_MASK);
1330 	writel(qm->error_mask, qm->io_base + QM_ABNORMAL_INT_SOURCE);
1333 	writel(err_info->ce, qm->io_base + QM_RAS_CE_ENABLE);
1334 	writel(QM_RAS_CE_TIMES_PER_IRQ, qm->io_base + QM_RAS_CE_THRESHOLD);
1335 	writel(err_info->nfe, qm->io_base + QM_RAS_NFE_ENABLE);
1336 	writel(err_info->fe, qm->io_base + QM_RAS_FE_ENABLE);
1346 	irq_unmask &= readl(qm->io_base + QM_ABNORMAL_INT_MASK);
1347 	writel(irq_unmask, qm->io_base + QM_ABNORMAL_INT_MASK);
1354 	irq_mask |= readl(qm->io_base + QM_ABNORMAL_INT_MASK);
1355 	writel(irq_mask, qm->io_base + QM_ABNORMAL_INT_MASK);
1365 	writel(qm->err_info.qm_shutdown_mask, qm->io_base + QM_OOO_SHUTDOWN_SEL);
1368 	irq_unmask &= readl(qm->io_base + QM_ABNORMAL_INT_MASK);
1369 	writel(irq_unmask, qm->io_base + QM_ABNORMAL_INT_MASK);
1376 	irq_mask |= readl(qm->io_base + QM_ABNORMAL_INT_MASK);
1377 	writel(irq_mask, qm->io_base + QM_ABNORMAL_INT_MASK);
1380 	writel(0x0, qm->io_base + QM_OOO_SHUTDOWN_SEL);
1399 			reg_val = readl(qm->io_base + QM_ABNORMAL_INF01);
1407 			reg_val = readl(qm->io_base + QM_ABNORMAL_INF00);
1418 			reg_val = readl(qm->io_base + QM_ABNORMAL_INF02);
1430 	tmp = readl(qm->io_base + QM_ABNORMAL_INT_STATUS);
1441 		writel(error_status, qm->io_base + QM_ABNORMAL_INT_SOURCE);
1442 		writel(qm->err_info.nfe, qm->io_base + QM_RAS_NFE_ENABLE);
1459 	*msg = readl(qm->io_base + QM_MB_CMD_DATA_ADDR_L) |
1460 		  ((u64)readl(qm->io_base + QM_MB_CMD_DATA_ADDR_H) << 32);
1472 		writeq(vf_mask, qm->io_base + QM_IFC_INT_SOURCE_P);
1474 	val = readl(qm->io_base + QM_IFC_INT_SOURCE_V);
1476 	writel(val, qm->io_base + QM_IFC_INT_SOURCE_V);
1522 		val = readq(qm->io_base + QM_IFC_INT_SOURCE_P);
1553 	val = readl(qm->io_base + QM_IFC_INT_CFG);
1556 	writel(val, qm->io_base + QM_IFC_INT_CFG);
1558 	val = readl(qm->io_base + QM_IFC_INT_SET_P);
1560 	writel(val, qm->io_base + QM_IFC_INT_SET_P);
1567 	val = readl(qm->io_base + QM_IFC_INT_SET_V);
1569 	writel(val, qm->io_base + QM_IFC_INT_SET_V);
1591 		val = readq(qm->io_base + QM_IFC_READY_STATUS);
1631 		val = readq(qm->io_base + QM_IFC_READY_STATUS);
1672 		val = readl(qm->io_base + QM_IFC_INT_SET_V);
1712 		if (readl(qm->io_base + QM_PEH_DFX_INFO0))
1741 	ret = readl_relaxed_poll_timeout(qm->io_base + QM_PEH_DFX_INFO0,
1747 	ret = readl_relaxed_poll_timeout(qm->io_base + QM_PEH_DFX_INFO1,
2226 	writel(0x1, qm->io_base + QM_CACHE_WB_START);
2227 	if (readl_relaxed_poll_timeout(qm->io_base + QM_CACHE_WB_DONE,
2805 	val = readl(qm->io_base + QM_IFC_INT_MASK);
2807 	writel(val, qm->io_base + QM_IFC_INT_MASK);
2821 	val = readl(qm->io_base + QM_IFC_INT_MASK);
2823 	writel(val, qm->io_base + QM_IFC_INT_MASK);
2833 	iounmap(qm->io_base);
2849 		writel(state, qm->io_base + QM_VF_STATE);
2972 	writel(0x0, qm->io_base + QM_VF_EQ_INT_MASK);
2973 	writel(0x0, qm->io_base + QM_VF_AEQ_INT_MASK);
2978 	writel(0x1, qm->io_base + QM_VF_EQ_INT_MASK);
2979 	writel(0x1, qm->io_base + QM_VF_AEQ_INT_MASK);
3504 	ret = readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
3510 	writel(0x1, qm->io_base + QM_VFT_CFG_OP_WR);
3511 	writel(SHAPER_VFT, qm->io_base + QM_VFT_CFG_TYPE);
3512 	writel(fun_index, qm->io_base + QM_VFT_CFG);
3514 	writel(0x0, qm->io_base + QM_VFT_CFG_RDY);
3515 	writel(0x1, qm->io_base + QM_VFT_CFG_OP_ENABLE);
3517 	ret = readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
3523 	shaper_vft = readl(qm->io_base + QM_VFT_CFG_DATA_L) |
3524 		  ((u64)readl(qm->io_base + QM_VFT_CFG_DATA_H) << 32);
3947 	writel(ACC_VENDOR_ID_VALUE, qm->io_base + QM_PEH_VENDOR_ID);
3948 	ret = readl_relaxed_poll_timeout(qm->io_base + QM_PEH_VENDOR_ID, val,
3956 	writel(PCI_VENDOR_ID_HUAWEI, qm->io_base + QM_PEH_VENDOR_ID);
3957 	ret = readl_relaxed_poll_timeout(qm->io_base + QM_PEH_VENDOR_ID, val,
4131 		nfe_enb = readl(qm->io_base + QM_RAS_NFE_ENABLE);
4133 		       qm->io_base + QM_RAS_NFE_ENABLE);
4134 		writel(QM_ECC_MBIT, qm->io_base + QM_ABNORMAL_INT_SET);
4167 	       qm->io_base + ACC_MASTER_GLOBAL_CTRL);
4170 	ret = readl_relaxed_poll_timeout(qm->io_base + ACC_MASTER_TRANS_RETURN,
4290 	value = readl(qm->io_base + ACC_AM_CFG_PORT_WR_EN);
4292 	       qm->io_base + ACC_AM_CFG_PORT_WR_EN);
4300 	writel(QM_ECC_MBIT, qm->io_base + QM_ABNORMAL_INT_SOURCE);
4303 	writel(ACC_ROB_ECC_ERR_MULTPL, qm->io_base + ACC_AM_ROB_ECC_INT_STS);
4318 	value = readl(qm->io_base + ACC_AM_CFG_PORT_WR_EN);
4320 	writel(value, qm->io_base + ACC_AM_CFG_PORT_WR_EN);
4680 	ret = readl_relaxed_poll_timeout(qm->io_base + QM_IFC_INT_SOURCE_V, val,
4783 		val = readq(qm->io_base + QM_IFC_INT_SOURCE_P);
5087 		val = readl(qm->io_base + QM_FUNC_CAPS_REG);
5122 	qm->io_base = ioremap(qm->phys_base, pci_resource_len(pdev, PCI_BAR_2));
5123 	if (!qm->io_base) {
5143 		qm->db_io_base = qm->io_base;
5157 	iounmap(qm->io_base);
5380 		writel(QM_DB_TIMEOUT_SET, qm->io_base + QM_DB_TIMEOUT_CFG);
5504 	       qm->io_base + ACC_MASTER_GLOBAL_CTRL);
5506 	ret = readl_relaxed_poll_timeout(qm->io_base + ACC_MASTER_TRANS_RETURN,
5548 	writel(QM_DB_TIMEOUT_SET, qm->io_base + QM_DB_TIMEOUT_CFG);