Lines Matching refs:desc
59 static void cc_setup_xcbc(struct ahash_request *areq, struct cc_hw_desc desc[],
62 static void cc_setup_cmac(struct ahash_request *areq, struct cc_hw_desc desc[],
104 unsigned int flow_mode, struct cc_hw_desc desc[],
107 static void cc_set_endianity(u32 mode, struct cc_hw_desc *desc)
111 set_bytes_swap(desc, 1);
113 set_cipher_config0(desc, HASH_DIGEST_RESULT_LITTLE_ENDIAN);
341 static int cc_fin_result(struct cc_hw_desc *desc, struct ahash_request *req,
350 hw_desc_init(&desc[idx]);
351 set_hash_cipher_mode(&desc[idx], ctx->hw_mode, ctx->hash_mode);
352 set_dout_dlli(&desc[idx], state->digest_result_dma_addr, digestsize,
354 set_queue_last_ind(ctx->drvdata, &desc[idx]);
355 set_flow_mode(&desc[idx], S_HASH_to_DOUT);
356 set_setup_mode(&desc[idx], SETUP_WRITE_STATE0);
357 set_cipher_config1(&desc[idx], HASH_PADDING_DISABLED);
358 cc_set_endianity(ctx->hash_mode, &desc[idx]);
364 static int cc_fin_hmac(struct cc_hw_desc *desc, struct ahash_request *req,
373 hw_desc_init(&desc[idx]);
374 set_cipher_mode(&desc[idx], ctx->hw_mode);
375 set_dout_dlli(&desc[idx], state->digest_buff_dma_addr, digestsize,
377 set_flow_mode(&desc[idx], S_HASH_to_DOUT);
378 cc_set_endianity(ctx->hash_mode, &desc[idx]);
379 set_setup_mode(&desc[idx], SETUP_WRITE_STATE0);
383 hw_desc_init(&desc[idx]);
384 set_cipher_mode(&desc[idx], ctx->hw_mode);
385 set_din_type(&desc[idx], DMA_DLLI, state->opad_digest_dma_addr,
387 set_flow_mode(&desc[idx], S_DIN_to_HASH);
388 set_setup_mode(&desc[idx], SETUP_LOAD_STATE0);
392 hw_desc_init(&desc[idx]);
393 set_cipher_mode(&desc[idx], ctx->hw_mode);
394 set_din_sram(&desc[idx],
397 set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED);
398 set_flow_mode(&desc[idx], S_DIN_to_HASH);
399 set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);
403 hw_desc_init(&desc[idx]);
404 set_din_no_dma(&desc[idx], 0, 0xfffff0);
405 set_dout_no_dma(&desc[idx], 0, 0, 1);
409 hw_desc_init(&desc[idx]);
410 set_din_type(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr,
412 set_flow_mode(&desc[idx], DIN_HASH);
430 struct cc_hw_desc desc[CC_MAX_HASH_SEQ_LEN];
467 hw_desc_init(&desc[idx]);
468 set_hash_cipher_mode(&desc[idx], ctx->hw_mode, ctx->hash_mode);
470 set_din_type(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr,
475 set_din_sram(&desc[idx], larval_digest_addr,
478 set_flow_mode(&desc[idx], S_DIN_to_HASH);
479 set_setup_mode(&desc[idx], SETUP_LOAD_STATE0);
483 hw_desc_init(&desc[idx]);
484 set_hash_cipher_mode(&desc[idx], ctx->hw_mode, ctx->hash_mode);
487 set_din_type(&desc[idx], DMA_DLLI,
491 set_din_const(&desc[idx], 0, ctx->hash_len);
493 set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED);
495 set_cipher_do(&desc[idx], DO_PAD);
497 set_flow_mode(&desc[idx], S_DIN_to_HASH);
498 set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);
501 cc_set_desc(state, ctx, DIN_HASH, desc, false, &idx);
505 hw_desc_init(&desc[idx]);
506 set_cipher_mode(&desc[idx], ctx->hw_mode);
507 set_dout_dlli(&desc[idx], state->digest_buff_dma_addr,
509 set_flow_mode(&desc[idx], S_HASH_to_DOUT);
510 set_setup_mode(&desc[idx], SETUP_WRITE_STATE1);
511 set_cipher_do(&desc[idx], DO_PAD);
514 idx = cc_fin_hmac(desc, req, idx);
517 idx = cc_fin_result(desc, req, idx);
519 rc = cc_send_request(ctx->drvdata, &cc_req, desc, idx, &req->base);
529 static int cc_restore_hash(struct cc_hw_desc *desc, struct cc_hash_ctx *ctx,
533 hw_desc_init(&desc[idx]);
534 set_hash_cipher_mode(&desc[idx], ctx->hw_mode, ctx->hash_mode);
535 set_din_type(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr,
537 set_flow_mode(&desc[idx], S_DIN_to_HASH);
538 set_setup_mode(&desc[idx], SETUP_LOAD_STATE0);
542 hw_desc_init(&desc[idx]);
543 set_hash_cipher_mode(&desc[idx], ctx->hw_mode, ctx->hash_mode);
544 set_cipher_config1(&desc[idx], HASH_PADDING_DISABLED);
545 set_din_type(&desc[idx], DMA_DLLI, state->digest_bytes_len_dma_addr,
547 set_flow_mode(&desc[idx], S_DIN_to_HASH);
548 set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);
551 cc_set_desc(state, ctx, DIN_HASH, desc, false, &idx);
566 struct cc_hw_desc desc[CC_MAX_HASH_SEQ_LEN];
602 idx = cc_restore_hash(desc, ctx, state, idx);
605 hw_desc_init(&desc[idx]);
606 set_hash_cipher_mode(&desc[idx], ctx->hw_mode, ctx->hash_mode);
607 set_dout_dlli(&desc[idx], state->digest_buff_dma_addr,
609 set_flow_mode(&desc[idx], S_HASH_to_DOUT);
610 set_setup_mode(&desc[idx], SETUP_WRITE_STATE0);
614 hw_desc_init(&desc[idx]);
615 set_hash_cipher_mode(&desc[idx], ctx->hw_mode, ctx->hash_mode);
616 set_dout_dlli(&desc[idx], state->digest_bytes_len_dma_addr,
618 set_queue_last_ind(ctx->drvdata, &desc[idx]);
619 set_flow_mode(&desc[idx], S_HASH_to_DOUT);
620 set_setup_mode(&desc[idx], SETUP_WRITE_STATE1);
623 rc = cc_send_request(ctx->drvdata, &cc_req, desc, idx, &req->base);
644 struct cc_hw_desc desc[CC_MAX_HASH_SEQ_LEN];
674 idx = cc_restore_hash(desc, ctx, state, idx);
677 hw_desc_init(&desc[idx]);
678 set_cipher_do(&desc[idx], DO_PAD);
679 set_hash_cipher_mode(&desc[idx], ctx->hw_mode, ctx->hash_mode);
680 set_dout_dlli(&desc[idx], state->digest_bytes_len_dma_addr,
682 set_setup_mode(&desc[idx], SETUP_WRITE_STATE1);
683 set_flow_mode(&desc[idx], S_HASH_to_DOUT);
687 idx = cc_fin_hmac(desc, req, idx);
689 idx = cc_fin_result(desc, req, idx);
691 rc = cc_send_request(ctx->drvdata, &cc_req, desc, idx, &req->base);
735 struct cc_hw_desc desc[CC_MAX_HASH_SEQ_LEN];
775 hw_desc_init(&desc[idx]);
776 set_cipher_mode(&desc[idx], ctx->hw_mode);
777 set_din_sram(&desc[idx], larval_addr,
779 set_flow_mode(&desc[idx], S_DIN_to_HASH);
780 set_setup_mode(&desc[idx], SETUP_LOAD_STATE0);
784 hw_desc_init(&desc[idx]);
785 set_cipher_mode(&desc[idx], ctx->hw_mode);
786 set_din_const(&desc[idx], 0, ctx->hash_len);
787 set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED);
788 set_flow_mode(&desc[idx], S_DIN_to_HASH);
789 set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);
792 hw_desc_init(&desc[idx]);
793 set_din_type(&desc[idx], DMA_DLLI,
796 set_flow_mode(&desc[idx], DIN_HASH);
800 hw_desc_init(&desc[idx]);
801 set_cipher_mode(&desc[idx], ctx->hw_mode);
802 set_dout_dlli(&desc[idx], ctx->opad_tmp_keys_dma_addr,
804 set_flow_mode(&desc[idx], S_HASH_to_DOUT);
805 set_setup_mode(&desc[idx], SETUP_WRITE_STATE0);
806 set_cipher_config1(&desc[idx], HASH_PADDING_DISABLED);
807 cc_set_endianity(ctx->hash_mode, &desc[idx]);
810 hw_desc_init(&desc[idx]);
811 set_din_const(&desc[idx], 0, (blocksize - digestsize));
812 set_flow_mode(&desc[idx], BYPASS);
813 set_dout_dlli(&desc[idx],
819 hw_desc_init(&desc[idx]);
820 set_din_type(&desc[idx], DMA_DLLI,
823 set_flow_mode(&desc[idx], BYPASS);
824 set_dout_dlli(&desc[idx], ctx->opad_tmp_keys_dma_addr,
829 hw_desc_init(&desc[idx]);
830 set_din_const(&desc[idx], 0,
832 set_flow_mode(&desc[idx], BYPASS);
833 set_dout_dlli(&desc[idx],
841 hw_desc_init(&desc[idx]);
842 set_din_const(&desc[idx], 0, blocksize);
843 set_flow_mode(&desc[idx], BYPASS);
844 set_dout_dlli(&desc[idx], (ctx->opad_tmp_keys_dma_addr),
849 rc = cc_send_sync_request(ctx->drvdata, &cc_req, desc, idx);
858 hw_desc_init(&desc[idx]);
859 set_cipher_mode(&desc[idx], ctx->hw_mode);
860 set_din_sram(&desc[idx], larval_addr, ctx->inter_digestsize);
861 set_flow_mode(&desc[idx], S_DIN_to_HASH);
862 set_setup_mode(&desc[idx], SETUP_LOAD_STATE0);
866 hw_desc_init(&desc[idx]);
867 set_cipher_mode(&desc[idx], ctx->hw_mode);
868 set_din_const(&desc[idx], 0, ctx->hash_len);
869 set_flow_mode(&desc[idx], S_DIN_to_HASH);
870 set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);
874 hw_desc_init(&desc[idx]);
875 set_xor_val(&desc[idx], hmac_pad_const[i]);
876 set_cipher_mode(&desc[idx], ctx->hw_mode);
877 set_flow_mode(&desc[idx], S_DIN_to_HASH);
878 set_setup_mode(&desc[idx], SETUP_LOAD_STATE1);
882 hw_desc_init(&desc[idx]);
883 set_din_type(&desc[idx], DMA_DLLI, ctx->opad_tmp_keys_dma_addr,
885 set_cipher_mode(&desc[idx], ctx->hw_mode);
886 set_xor_active(&desc[idx]);
887 set_flow_mode(&desc[idx], DIN_HASH);
893 hw_desc_init(&desc[idx]);
894 set_cipher_mode(&desc[idx], ctx->hw_mode);
896 set_dout_dlli(&desc[idx], ctx->opad_tmp_keys_dma_addr,
899 set_dout_dlli(&desc[idx], ctx->digest_buff_dma_addr,
901 set_flow_mode(&desc[idx], S_HASH_to_DOUT);
902 set_setup_mode(&desc[idx], SETUP_WRITE_STATE0);
906 rc = cc_send_sync_request(ctx->drvdata, &cc_req, desc, idx);
929 struct cc_hw_desc desc[CC_MAX_HASH_SEQ_LEN];
961 hw_desc_init(&desc[idx]);
962 set_din_type(&desc[idx], DMA_DLLI, ctx->key_params.key_dma_addr,
964 set_cipher_mode(&desc[idx], DRV_CIPHER_ECB);
965 set_cipher_config0(&desc[idx], DRV_CRYPTO_DIRECTION_ENCRYPT);
966 set_key_size_aes(&desc[idx], keylen);
967 set_flow_mode(&desc[idx], S_DIN_to_AES);
968 set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);
971 hw_desc_init(&desc[idx]);
972 set_din_const(&desc[idx], 0x01010101, CC_AES_128_BIT_KEY_SIZE);
973 set_flow_mode(&desc[idx], DIN_AES_DOUT);
974 set_dout_dlli(&desc[idx],
979 hw_desc_init(&desc[idx]);
980 set_din_const(&desc[idx], 0x02020202, CC_AES_128_BIT_KEY_SIZE);
981 set_flow_mode(&desc[idx], DIN_AES_DOUT);
982 set_dout_dlli(&desc[idx],
987 hw_desc_init(&desc[idx]);
988 set_din_const(&desc[idx], 0x03030303, CC_AES_128_BIT_KEY_SIZE);
989 set_flow_mode(&desc[idx], DIN_AES_DOUT);
990 set_dout_dlli(&desc[idx],
995 rc = cc_send_sync_request(ctx->drvdata, &cc_req, desc, idx);
1158 struct cc_hw_desc desc[CC_MAX_HASH_SEQ_LEN];
1189 cc_setup_xcbc(req, desc, &idx);
1191 cc_setup_cmac(req, desc, &idx);
1193 cc_set_desc(state, ctx, DIN_AES_DOUT, desc, true, &idx);
1196 hw_desc_init(&desc[idx]);
1197 set_cipher_mode(&desc[idx], ctx->hw_mode);
1198 set_dout_dlli(&desc[idx], state->digest_buff_dma_addr,
1200 set_queue_last_ind(ctx->drvdata, &desc[idx]);
1201 set_flow_mode(&desc[idx], S_AES_to_DOUT);
1202 set_setup_mode(&desc[idx], SETUP_WRITE_STATE0);
1209 rc = cc_send_request(ctx->drvdata, &cc_req, desc, idx, &req->base);
1225 struct cc_hw_desc desc[CC_MAX_HASH_SEQ_LEN];
1269 hw_desc_init(&desc[idx]);
1270 set_cipher_mode(&desc[idx], DRV_CIPHER_ECB);
1271 set_cipher_config0(&desc[idx], DRV_CRYPTO_DIRECTION_DECRYPT);
1272 set_din_type(&desc[idx], DMA_DLLI,
1275 set_key_size_aes(&desc[idx], key_len);
1276 set_flow_mode(&desc[idx], S_DIN_to_AES);
1277 set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);
1283 hw_desc_init(&desc[idx]);
1284 set_din_type(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr,
1286 set_dout_dlli(&desc[idx], state->digest_buff_dma_addr,
1288 set_flow_mode(&desc[idx], DIN_AES_DOUT);
1292 hw_desc_init(&desc[idx]);
1293 set_din_no_dma(&desc[idx], 0, 0xfffff0);
1294 set_dout_no_dma(&desc[idx], 0, 0, 1);
1299 cc_setup_xcbc(req, desc, &idx);
1301 cc_setup_cmac(req, desc, &idx);
1304 hw_desc_init(&desc[idx]);
1305 set_cipher_mode(&desc[idx], ctx->hw_mode);
1306 set_key_size_aes(&desc[idx], key_len);
1307 set_cmac_size0_mode(&desc[idx]);
1308 set_flow_mode(&desc[idx], S_DIN_to_AES);
1311 cc_set_desc(state, ctx, DIN_AES_DOUT, desc, false, &idx);
1313 hw_desc_init(&desc[idx]);
1314 set_din_const(&desc[idx], 0x00, CC_AES_BLOCK_SIZE);
1315 set_flow_mode(&desc[idx], DIN_AES_DOUT);
1320 hw_desc_init(&desc[idx]);
1321 set_dout_dlli(&desc[idx], state->digest_result_dma_addr,
1323 set_queue_last_ind(ctx->drvdata, &desc[idx]);
1324 set_flow_mode(&desc[idx], S_AES_to_DOUT);
1325 set_setup_mode(&desc[idx], SETUP_WRITE_STATE0);
1326 set_cipher_mode(&desc[idx], ctx->hw_mode);
1329 rc = cc_send_request(ctx->drvdata, &cc_req, desc, idx, &req->base);
1346 struct cc_hw_desc desc[CC_MAX_HASH_SEQ_LEN];
1383 cc_setup_xcbc(req, desc, &idx);
1386 cc_setup_cmac(req, desc, &idx);
1390 hw_desc_init(&desc[idx]);
1391 set_cipher_mode(&desc[idx], ctx->hw_mode);
1392 set_key_size_aes(&desc[idx], key_len);
1393 set_cmac_size0_mode(&desc[idx]);
1394 set_flow_mode(&desc[idx], S_DIN_to_AES);
1397 cc_set_desc(state, ctx, DIN_AES_DOUT, desc, false, &idx);
1401 hw_desc_init(&desc[idx]);
1402 set_dout_dlli(&desc[idx], state->digest_result_dma_addr,
1404 set_queue_last_ind(ctx->drvdata, &desc[idx]);
1405 set_flow_mode(&desc[idx], S_AES_to_DOUT);
1406 set_setup_mode(&desc[idx], SETUP_WRITE_STATE0);
1407 set_cipher_mode(&desc[idx], ctx->hw_mode);
1410 rc = cc_send_request(ctx->drvdata, &cc_req, desc, idx, &req->base);
1428 struct cc_hw_desc desc[CC_MAX_HASH_SEQ_LEN];
1461 cc_setup_xcbc(req, desc, &idx);
1464 cc_setup_cmac(req, desc, &idx);
1468 hw_desc_init(&desc[idx]);
1469 set_cipher_mode(&desc[idx], ctx->hw_mode);
1470 set_key_size_aes(&desc[idx], key_len);
1471 set_cmac_size0_mode(&desc[idx]);
1472 set_flow_mode(&desc[idx], S_DIN_to_AES);
1475 cc_set_desc(state, ctx, DIN_AES_DOUT, desc, false, &idx);
1479 hw_desc_init(&desc[idx]);
1480 set_dout_dlli(&desc[idx], state->digest_result_dma_addr,
1482 set_queue_last_ind(ctx->drvdata, &desc[idx]);
1483 set_flow_mode(&desc[idx], S_AES_to_DOUT);
1484 set_setup_mode(&desc[idx], SETUP_WRITE_STATE0);
1485 set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT);
1486 set_cipher_mode(&desc[idx], ctx->hw_mode);
1489 rc = cc_send_request(ctx->drvdata, &cc_req, desc, idx, &req->base);
2072 static void cc_setup_xcbc(struct ahash_request *areq, struct cc_hw_desc desc[],
2081 hw_desc_init(&desc[idx]);
2082 set_din_type(&desc[idx], DMA_DLLI, (ctx->opad_tmp_keys_dma_addr +
2085 set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);
2086 set_hash_cipher_mode(&desc[idx], DRV_CIPHER_XCBC_MAC, ctx->hash_mode);
2087 set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT);
2088 set_key_size_aes(&desc[idx], CC_AES_128_BIT_KEY_SIZE);
2089 set_flow_mode(&desc[idx], S_DIN_to_AES);
2093 hw_desc_init(&desc[idx]);
2094 set_din_type(&desc[idx], DMA_DLLI,
2097 set_setup_mode(&desc[idx], SETUP_LOAD_STATE1);
2098 set_cipher_mode(&desc[idx], DRV_CIPHER_XCBC_MAC);
2099 set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT);
2100 set_key_size_aes(&desc[idx], CC_AES_128_BIT_KEY_SIZE);
2101 set_flow_mode(&desc[idx], S_DIN_to_AES);
2105 hw_desc_init(&desc[idx]);
2106 set_din_type(&desc[idx], DMA_DLLI,
2109 set_setup_mode(&desc[idx], SETUP_LOAD_STATE2);
2110 set_cipher_mode(&desc[idx], DRV_CIPHER_XCBC_MAC);
2111 set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT);
2112 set_key_size_aes(&desc[idx], CC_AES_128_BIT_KEY_SIZE);
2113 set_flow_mode(&desc[idx], S_DIN_to_AES);
2117 hw_desc_init(&desc[idx]);
2118 set_din_type(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr,
2120 set_setup_mode(&desc[idx], SETUP_LOAD_STATE0);
2121 set_cipher_mode(&desc[idx], DRV_CIPHER_XCBC_MAC);
2122 set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT);
2123 set_key_size_aes(&desc[idx], CC_AES_128_BIT_KEY_SIZE);
2124 set_flow_mode(&desc[idx], S_DIN_to_AES);
2129 static void cc_setup_cmac(struct ahash_request *areq, struct cc_hw_desc desc[],
2138 hw_desc_init(&desc[idx]);
2139 set_din_type(&desc[idx], DMA_DLLI, ctx->opad_tmp_keys_dma_addr,
2142 set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);
2143 set_cipher_mode(&desc[idx], DRV_CIPHER_CMAC);
2144 set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT);
2145 set_key_size_aes(&desc[idx], ctx->key_params.keylen);
2146 set_flow_mode(&desc[idx], S_DIN_to_AES);
2150 hw_desc_init(&desc[idx]);
2151 set_din_type(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr,
2153 set_setup_mode(&desc[idx], SETUP_LOAD_STATE0);
2154 set_cipher_mode(&desc[idx], DRV_CIPHER_CMAC);
2155 set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT);
2156 set_key_size_aes(&desc[idx], ctx->key_params.keylen);
2157 set_flow_mode(&desc[idx], S_DIN_to_AES);
2164 struct cc_hw_desc desc[], bool is_not_last_data,
2171 hw_desc_init(&desc[idx]);
2172 set_din_type(&desc[idx], DMA_DLLI,
2175 set_flow_mode(&desc[idx], flow_mode);
2184 hw_desc_init(&desc[idx]);
2185 set_din_type(&desc[idx], DMA_DLLI,
2188 set_dout_sram(&desc[idx], ctx->drvdata->mlli_sram_addr,
2190 set_flow_mode(&desc[idx], BYPASS);
2193 hw_desc_init(&desc[idx]);
2194 set_din_type(&desc[idx], DMA_MLLI,
2197 set_flow_mode(&desc[idx], flow_mode);
2201 set_din_not_last_indication(&desc[(idx - 1)]);
2202 /* return updated desc sequence size */