cavium/cpt/cptpf_main.c

122 static int cpt_load_microcode(struct cpt_device *cpt, struct microcode *mcode)
128 	if (!mcode || !mcode->code) {
129 		dev_err(dev, "Either the mcode is null or data is NULL\n");
133 	if (mcode->code_size == 0) {
141 	if (mcode->is_ae) {
151 		if (mcode->core_mask & (1 << shift)) {
154 					(u64)mcode->phys_base);
160 static int do_cpt_init(struct cpt_device *cpt, struct microcode *mcode)
169 	/* Calculate mcode group and coremasks */
170 	if (mcode->is_ae) {
171 		if (mcode->num_cores > cpt->max_ae_cores) {
182 		mcode->group = cpt->next_group;
184 		mcode->core_mask = GENMASK(mcode->num_cores, 0);
185 		cpt_disable_cores(cpt, mcode->core_mask, AE_TYPES,
186 				  mcode->group);
188 		ret = cpt_load_microcode(cpt, mcode);
191 				mcode->version);
195 		/* Configure group mask for the mcode */
196 		cpt_configure_group(cpt, mcode->group, mcode->core_mask,
199 		cpt_enable_cores(cpt, mcode->core_mask, AE_TYPES);
201 		if (mcode->num_cores > cpt->max_se_cores) {
211 		mcode->group = cpt->next_group;
213 		mcode->core_mask = GENMASK(mcode->num_cores, 0);
214 		cpt_disable_cores(cpt, mcode->core_mask, SE_TYPES,
215 				  mcode->group);
217 		ret = cpt_load_microcode(cpt, mcode);
220 				mcode->version);
224 		/* Configure group mask for the mcode */
225 		cpt_configure_group(cpt, mcode->group, mcode->core_mask,
228 		cpt_enable_cores(cpt, mcode->core_mask, SE_TYPES);
257 	struct microcode *mcode;
265 	mcode = &cpt->mcode[cpt->next_mc_idx];
266 	memcpy(mcode->version, (u8 *)fw_entry->data, CPT_UCODE_VERSION_SZ);
272 	mcode->code_size = code_length * 2;
274 	mcode->is_ae = is_ae;
275 	mcode->core_mask = 0ULL;
276 	mcode->num_cores = is_ae ? 6 : 10;
279 	mcode->code = dma_alloc_coherent(&cpt->pdev->dev, mcode->code_size,
280 					 &mcode->phys_base, GFP_KERNEL);
281 	if (!mcode->code) {
287 	memcpy((void *)mcode->code, (void *)(fw_entry->data + sizeof(*ucode)),
288 	       mcode->code_size);
291 	for (j = 0; j < (mcode->code_size / 8); j++)
292 		((__be64 *)mcode->code)[j] = cpu_to_be64(((u64 *)mcode->code)[j]);
294 	for (j = 0; j < (mcode->code_size / 2); j++)
295 		((__be16 *)mcode->code)[j] = cpu_to_be16(((u16 *)mcode->code)[j]);
297 	dev_dbg(dev, "mcode->code_size = %u\n", mcode->code_size);
298 	dev_dbg(dev, "mcode->is_ae = %u\n", mcode->is_ae);
299 	dev_dbg(dev, "mcode->num_cores = %u\n", mcode->num_cores);
300 	dev_dbg(dev, "mcode->code = %llx\n", (u64)mcode->code);
301 	dev_dbg(dev, "mcode->phys_base = %llx\n", mcode->phys_base);
303 	ret = do_cpt_init(cpt, mcode);
309 	dev_info(dev, "Microcode Loaded %s\n", mcode->version);
310 	mcode->is_mc_valid = 1;
417 		struct microcode *mcode = &cpt->mcode[grp];
419 		if (cpt->mcode[grp].code)
420 			dma_free_coherent(&cpt->pdev->dev, mcode->code_size,
421 					  mcode->code, mcode->phys_base);
422 		mcode->code = NULL;