crypto/caam/jr.c

87 	if (rd_reg32(&jrp->rregs->jrintstatus) & JRINT_ERR_HALT_INPROGRESS)
91 	clrsetbits_32(&jrp->rregs->jrintstatus, JRINT_ERR_HALT_MASK, 0);
94 	wr_reg32(&jrp->rregs->jrcommand, jrcr_bits);
97 	while (((rd_reg32(&jrp->rregs->jrintstatus) & JRINT_ERR_HALT_MASK) ==
101 	if ((rd_reg32(&jrp->rregs->jrintstatus) & JRINT_ERR_HALT_MASK) !=
125 	u32 halt_status = rd_reg32(&jrp->rregs->jrintstatus) &
133 	clrsetbits_32(&jrp->rregs->jrintstatus, 0, JRINT_ERR_HALT_COMPLETE);
147 	clrsetbits_32(&jrp->rregs->rconfig_lo, 0, JRCFG_IMSK);
153 	wr_reg32(&jrp->rregs->jrcommand, JRCR_RESET);
154 	while ((rd_reg32(&jrp->rregs->jrcommand) & JRCR_RESET) && --timeout)
163 	clrsetbits_32(&jrp->rregs->rconfig_lo, JRCFG_IMSK, 0);
231 	irqstate = rd_reg32(&jrp->rregs->jrintstatus);
246 	clrsetbits_32(&jrp->rregs->rconfig_lo, 0, JRCFG_IMSK);
249 	wr_reg32(&jrp->rregs->jrintstatus, irqstate);
271 	       (outring_used = rd_reg32(&jrp->rregs->outring_used))) {
313 		wr_reg32(&jrp->rregs->outring_rmvd, 1);
339 		clrsetbits_32(&jrp->rregs->rconfig_lo, JRCFG_IMSK, 0);
485 	wr_reg32(&jrp->rregs->inpring_jobadd, 1);
489 		jrp->inpring_avail = rd_reg32(&jrp->rregs->inpring_avail);
502 	wr_reg64(&jrp->rregs->inpring_base, inpbusaddr);
503 	wr_reg64(&jrp->rregs->outring_base, outbusaddr);
504 	wr_reg32(&jrp->rregs->inpring_size, JOBR_DEPTH);
505 	wr_reg32(&jrp->rregs->outring_size, JOBR_DEPTH);
508 	clrsetbits_32(&jrp->rregs->rconfig_lo, 0, JOBR_INTC |
622 	jrpriv->rregs = (struct caam_job_ring __iomem __force *)ctrl;
688 	jrp->state.inpbusaddr = rd_reg64(&jrp->rregs->inpring_base);
689 	jrp->state.outbusaddr = rd_reg64(&jrp->rregs->outring_base);
716 		clrsetbits_32(&jrpriv->rregs->rconfig_lo, 0, JRCFG_IMSK);
751 		inp_addr = rd_reg64(&jrpriv->rregs->inpring_base);
765 				clrsetbits_32(&jrpriv->rregs->rconfig_lo,