Lines Matching refs:ss
3 * sun8i-ss-core.c - hardware cryptographic offloader for
30 #include "sun8i-ss.h"
62 int sun8i_ss_get_engine_number(struct sun8i_ss_dev *ss)
64 return atomic_inc_return(&ss->flow) % MAXFLOW;
67 int sun8i_ss_run_task(struct sun8i_ss_dev *ss, struct sun8i_cipher_req_ctx *rctx,
76 ss->flows[flow].stat_req++;
107 mutex_lock(&ss->mlock);
108 writel(rctx->p_key, ss->base + SS_KEY_ADR_REG);
113 writel(rctx->p_iv[0], ss->base + SS_IV_ADR_REG);
115 writel(rctx->t_dst[i - 1].addr + rctx->t_dst[i - 1].len * 4 - ivlen, ss->base + SS_IV_ADR_REG);
117 writel(rctx->p_iv[i], ss->base + SS_IV_ADR_REG);
121 dev_dbg(ss->dev,
128 writel(rctx->t_src[i].addr, ss->base + SS_SRC_ADR_REG);
129 writel(rctx->t_dst[i].addr, ss->base + SS_DST_ADR_REG);
130 writel(rctx->t_src[i].len, ss->base + SS_LEN_ADR_REG);
132 reinit_completion(&ss->flows[flow].complete);
133 ss->flows[flow].status = 0;
136 writel(v, ss->base + SS_CTL_REG);
137 mutex_unlock(&ss->mlock);
138 wait_for_completion_interruptible_timeout(&ss->flows[flow].complete,
140 if (ss->flows[flow].status == 0) {
141 dev_err(ss->dev, "DMA timeout for %s\n", name);
151 struct sun8i_ss_dev *ss = (struct sun8i_ss_dev *)data;
155 p = readl(ss->base + SS_INT_STA_REG);
158 writel(BIT(flow), ss->base + SS_INT_STA_REG);
159 ss->flows[flow].status = 1;
160 complete(&ss->flows[flow].complete);
175 .cra_driver_name = "cbc-aes-sun8i-ss",
205 .cra_driver_name = "ecb-aes-sun8i-ss",
234 .cra_driver_name = "cbc-des3-sun8i-ss",
264 .cra_driver_name = "ecb-des3-sun8i-ss",
292 .cra_driver_name = "sun8i-ss-prng",
323 .cra_driver_name = "md5-sun8i-ss",
355 .cra_driver_name = "sha1-sun8i-ss",
387 .cra_driver_name = "sha224-sun8i-ss",
419 .cra_driver_name = "sha256-sun8i-ss",
452 .cra_driver_name = "hmac-sha1-sun8i-ss",
472 struct sun8i_ss_dev *ss __maybe_unused = seq->private;
478 ss->flows[i].stat_req);
484 if (!ss_algs[i].ss)
533 static void sun8i_ss_free_flows(struct sun8i_ss_dev *ss, int i)
536 crypto_engine_exit(ss->flows[i].engine);
544 static int allocate_flows(struct sun8i_ss_dev *ss)
548 ss->flows = devm_kcalloc(ss->dev, MAXFLOW, sizeof(struct sun8i_ss_flow),
550 if (!ss->flows)
554 init_completion(&ss->flows[i].complete);
556 ss->flows[i].biv = devm_kmalloc(ss->dev, AES_BLOCK_SIZE,
558 if (!ss->flows[i].biv) {
564 ss->flows[i].iv[j] = devm_kmalloc(ss->dev, AES_BLOCK_SIZE,
566 if (!ss->flows[i].iv[j]) {
573 ss->flows[i].pad = devm_kmalloc(ss->dev, MAX_PAD_SIZE,
575 if (!ss->flows[i].pad) {
579 ss->flows[i].result =
580 devm_kmalloc(ss->dev, max(SHA256_DIGEST_SIZE,
583 if (!ss->flows[i].result) {
588 ss->flows[i].engine = crypto_engine_alloc_init(ss->dev, true);
589 if (!ss->flows[i].engine) {
590 dev_err(ss->dev, "Cannot allocate engine\n");
595 err = crypto_engine_start(ss->flows[i].engine);
597 dev_err(ss->dev, "Cannot start engine\n");
603 sun8i_ss_free_flows(ss, i);
613 struct sun8i_ss_dev *ss = dev_get_drvdata(dev);
616 reset_control_assert(ss->reset);
618 clk_disable_unprepare(ss->ssclks[i]);
624 struct sun8i_ss_dev *ss = dev_get_drvdata(dev);
628 if (!ss->variant->ss_clks[i].name)
630 err = clk_prepare_enable(ss->ssclks[i]);
632 dev_err(ss->dev, "Cannot prepare_enable %s\n",
633 ss->variant->ss_clks[i].name);
637 err = reset_control_deassert(ss->reset);
639 dev_err(ss->dev, "Cannot deassert reset control\n");
643 writel(BIT(0) | BIT(1), ss->base + SS_INT_CTL_REG);
655 static int sun8i_ss_pm_init(struct sun8i_ss_dev *ss)
659 pm_runtime_use_autosuspend(ss->dev);
660 pm_runtime_set_autosuspend_delay(ss->dev, 2000);
662 err = pm_runtime_set_suspended(ss->dev);
665 pm_runtime_enable(ss->dev);
669 static void sun8i_ss_pm_exit(struct sun8i_ss_dev *ss)
671 pm_runtime_disable(ss->dev);
674 static int sun8i_ss_register_algs(struct sun8i_ss_dev *ss)
680 ss_algs[i].ss = ss;
684 ss_method = ss->variant->alg_cipher[id];
686 dev_info(ss->dev,
689 ss_algs[i].ss = NULL;
693 ss_method = ss->variant->op_mode[id];
695 dev_info(ss->dev, "DEBUG: Blockmode of %s not supported\n",
697 ss_algs[i].ss = NULL;
700 dev_info(ss->dev, "DEBUG: Register %s\n",
704 dev_err(ss->dev, "Fail to register %s\n",
706 ss_algs[i].ss = NULL;
713 dev_err(ss->dev, "Fail to register %s\n",
715 ss_algs[i].ss = NULL;
720 ss_method = ss->variant->alg_hash[id];
722 dev_info(ss->dev,
725 ss_algs[i].ss = NULL;
728 dev_info(ss->dev, "Register %s\n",
732 dev_err(ss->dev, "ERROR: Fail to register %s\n",
734 ss_algs[i].ss = NULL;
739 ss_algs[i].ss = NULL;
740 dev_err(ss->dev, "ERROR: tried to register an unknown algo\n");
746 static void sun8i_ss_unregister_algs(struct sun8i_ss_dev *ss)
751 if (!ss_algs[i].ss)
755 dev_info(ss->dev, "Unregister %d %s\n", i,
760 dev_info(ss->dev, "Unregister %d %s\n", i,
765 dev_info(ss->dev, "Unregister %d %s\n", i,
773 static int sun8i_ss_get_clks(struct sun8i_ss_dev *ss)
779 if (!ss->variant->ss_clks[i].name)
781 ss->ssclks[i] = devm_clk_get(ss->dev, ss->variant->ss_clks[i].name);
782 if (IS_ERR(ss->ssclks[i])) {
783 err = PTR_ERR(ss->ssclks[i]);
784 dev_err(ss->dev, "Cannot get %s SS clock err=%d\n",
785 ss->variant->ss_clks[i].name, err);
788 cr = clk_get_rate(ss->ssclks[i]);
791 if (ss->variant->ss_clks[i].freq > 0 &&
792 cr != ss->variant->ss_clks[i].freq) {
793 dev_info(ss->dev, "Set %s clock to %lu (%lu Mhz) from %lu (%lu Mhz)\n",
794 ss->variant->ss_clks[i].name,
795 ss->variant->ss_clks[i].freq,
796 ss->variant->ss_clks[i].freq / 1000000,
798 err = clk_set_rate(ss->ssclks[i], ss->variant->ss_clks[i].freq);
800 dev_err(ss->dev, "Fail to set %s clk speed to %lu hz\n",
801 ss->variant->ss_clks[i].name,
802 ss->variant->ss_clks[i].freq);
804 if (ss->variant->ss_clks[i].max_freq > 0 &&
805 cr > ss->variant->ss_clks[i].max_freq)
806 dev_warn(ss->dev, "Frequency for %s (%lu hz) is higher than datasheet's recommendation (%lu hz)",
807 ss->variant->ss_clks[i].name, cr,
808 ss->variant->ss_clks[i].max_freq);
815 struct sun8i_ss_dev *ss;
819 ss = devm_kzalloc(&pdev->dev, sizeof(*ss), GFP_KERNEL);
820 if (!ss)
823 ss->dev = &pdev->dev;
824 platform_set_drvdata(pdev, ss);
826 ss->variant = of_device_get_match_data(&pdev->dev);
827 if (!ss->variant) {
832 ss->base = devm_platform_ioremap_resource(pdev, 0);
833 if (IS_ERR(ss->base))
834 return PTR_ERR(ss->base);
836 err = sun8i_ss_get_clks(ss);
844 ss->reset = devm_reset_control_get(&pdev->dev, NULL);
845 if (IS_ERR(ss->reset))
846 return dev_err_probe(&pdev->dev, PTR_ERR(ss->reset),
849 mutex_init(&ss->mlock);
851 err = allocate_flows(ss);
855 err = sun8i_ss_pm_init(ss);
859 err = devm_request_irq(&pdev->dev, irq, ss_irq_handler, 0, "sun8i-ss", ss);
861 dev_err(ss->dev, "Cannot request SecuritySystem IRQ (err=%d)\n", err);
865 err = sun8i_ss_register_algs(ss);
869 err = pm_runtime_resume_and_get(ss->dev);
873 v = readl(ss->base + SS_CTL_REG);
878 pm_runtime_put_sync(ss->dev);
885 dbgfs_dir = debugfs_create_dir("sun8i-ss", NULL);
887 dbgfs_dir, ss,
891 ss->dbgfs_dir = dbgfs_dir;
892 ss->dbgfs_stats = dbgfs_stats;
898 sun8i_ss_unregister_algs(ss);
900 sun8i_ss_pm_exit(ss);
902 sun8i_ss_free_flows(ss, MAXFLOW - 1);
908 struct sun8i_ss_dev *ss = platform_get_drvdata(pdev);
910 sun8i_ss_unregister_algs(ss);
913 debugfs_remove_recursive(ss->dbgfs_dir);
916 sun8i_ss_free_flows(ss, MAXFLOW - 1);
918 sun8i_ss_pm_exit(ss);
934 .name = "sun8i-ss",