Lines Matching refs:ce
3 * sun8i-ce-core.c - hardware cryptographic offloader for
31 #include "sun8i-ce.h"
153 int sun8i_ce_get_engine_number(struct sun8i_ce_dev *ce)
155 return atomic_inc_return(&ce->flow) % (MAXFLOW - 1);
158 int sun8i_ce_run_task(struct sun8i_ce_dev *ce, int flow, const char *name)
162 struct ce_task *cet = ce->chanlist[flow].tl;
165 ce->chanlist[flow].stat_req++;
168 mutex_lock(&ce->mlock);
170 v = readl(ce->base + CE_ICR);
172 writel(v, ce->base + CE_ICR);
174 reinit_completion(&ce->chanlist[flow].complete);
175 writel(ce->chanlist[flow].t_phy, ce->base + CE_TDQ);
177 ce->chanlist[flow].status = 0;
184 v = 1 | ((le32_to_cpu(ce->chanlist[flow].tl->t_common_ctl) & 0x7F) << 8);
185 writel(v, ce->base + CE_TLR);
186 mutex_unlock(&ce->mlock);
188 wait_for_completion_interruptible_timeout(&ce->chanlist[flow].complete,
189 msecs_to_jiffies(ce->chanlist[flow].timeout));
191 if (ce->chanlist[flow].status == 0) {
192 dev_err(ce->dev, "DMA timeout for %s (tm=%d) on flow %d\n", name,
193 ce->chanlist[flow].timeout, flow);
199 v = readl(ce->base + CE_ESR);
200 switch (ce->variant->esr) {
204 dev_err(ce->dev, "CE ERROR: %x for flow %x\n", v, flow);
210 dev_err(ce->dev, "CE ERROR: algorithm not supported\n");
212 dev_err(ce->dev, "CE ERROR: data length error\n");
214 dev_err(ce->dev, "CE ERROR: keysram access error for AES\n");
223 dev_err(ce->dev, "CE ERROR: %x for flow %x\n", v, flow);
229 dev_err(ce->dev, "CE ERROR: algorithm not supported\n");
231 dev_err(ce->dev, "CE ERROR: data length error\n");
233 dev_err(ce->dev, "CE ERROR: keysram access error for AES\n");
239 dev_err(ce->dev, "CE ERROR: %x for flow %x\n", v, flow);
245 dev_err(ce->dev, "CE ERROR: algorithm not supported\n");
247 dev_err(ce->dev, "CE ERROR: data length error\n");
249 dev_err(ce->dev, "CE ERROR: keysram access error for AES\n");
251 dev_err(ce->dev, "CE ERROR: address invalid\n");
253 dev_err(ce->dev, "CE ERROR: key ladder configuration error\n");
262 struct sun8i_ce_dev *ce = (struct sun8i_ce_dev *)data;
266 p = readl(ce->base + CE_ISR);
269 writel(BIT(flow), ce->base + CE_ISR);
270 ce->chanlist[flow].status = 1;
271 complete(&ce->chanlist[flow].complete);
286 .cra_driver_name = "cbc-aes-sun8i-ce",
316 .cra_driver_name = "ecb-aes-sun8i-ce",
345 .cra_driver_name = "cbc-des3-sun8i-ce",
375 .cra_driver_name = "ecb-des3-sun8i-ce",
415 .cra_driver_name = "md5-sun8i-ce",
448 .cra_driver_name = "sha1-sun8i-ce",
480 .cra_driver_name = "sha224-sun8i-ce",
512 .cra_driver_name = "sha256-sun8i-ce",
544 .cra_driver_name = "sha384-sun8i-ce",
576 .cra_driver_name = "sha512-sun8i-ce",
598 .cra_driver_name = "sun8i-ce-prng",
615 struct sun8i_ce_dev *ce __maybe_unused = seq->private;
621 ce->chanlist[i].stat_req);
627 if (!ce_algs[i].ce)
681 ce->hwrng_stat_req, ce->hwrng_stat_bytes);
688 static void sun8i_ce_free_chanlist(struct sun8i_ce_dev *ce, int i)
691 crypto_engine_exit(ce->chanlist[i].engine);
692 if (ce->chanlist[i].tl)
693 dma_free_coherent(ce->dev, sizeof(struct ce_task),
694 ce->chanlist[i].tl,
695 ce->chanlist[i].t_phy);
703 static int sun8i_ce_allocate_chanlist(struct sun8i_ce_dev *ce)
707 ce->chanlist = devm_kcalloc(ce->dev, MAXFLOW,
709 if (!ce->chanlist)
713 init_completion(&ce->chanlist[i].complete);
715 ce->chanlist[i].engine = crypto_engine_alloc_init(ce->dev, true);
716 if (!ce->chanlist[i].engine) {
717 dev_err(ce->dev, "Cannot allocate engine\n");
722 err = crypto_engine_start(ce->chanlist[i].engine);
724 dev_err(ce->dev, "Cannot start engine\n");
727 ce->chanlist[i].tl = dma_alloc_coherent(ce->dev,
729 &ce->chanlist[i].t_phy,
731 if (!ce->chanlist[i].tl) {
732 dev_err(ce->dev, "Cannot get DMA memory for task %d\n",
737 ce->chanlist[i].bounce_iv = devm_kmalloc(ce->dev, AES_BLOCK_SIZE,
739 if (!ce->chanlist[i].bounce_iv) {
743 ce->chanlist[i].backup_iv = devm_kmalloc(ce->dev, AES_BLOCK_SIZE,
745 if (!ce->chanlist[i].backup_iv) {
752 sun8i_ce_free_chanlist(ce, i);
762 struct sun8i_ce_dev *ce = dev_get_drvdata(dev);
765 reset_control_assert(ce->reset);
767 clk_disable_unprepare(ce->ceclks[i]);
773 struct sun8i_ce_dev *ce = dev_get_drvdata(dev);
777 if (!ce->variant->ce_clks[i].name)
779 err = clk_prepare_enable(ce->ceclks[i]);
781 dev_err(ce->dev, "Cannot prepare_enable %s\n",
782 ce->variant->ce_clks[i].name);
786 err = reset_control_deassert(ce->reset);
788 dev_err(ce->dev, "Cannot deassert reset control\n");
801 static int sun8i_ce_pm_init(struct sun8i_ce_dev *ce)
805 pm_runtime_use_autosuspend(ce->dev);
806 pm_runtime_set_autosuspend_delay(ce->dev, 2000);
808 err = pm_runtime_set_suspended(ce->dev);
811 pm_runtime_enable(ce->dev);
815 static void sun8i_ce_pm_exit(struct sun8i_ce_dev *ce)
817 pm_runtime_disable(ce->dev);
820 static int sun8i_ce_get_clks(struct sun8i_ce_dev *ce)
826 if (!ce->variant->ce_clks[i].name)
828 ce->ceclks[i] = devm_clk_get(ce->dev, ce->variant->ce_clks[i].name);
829 if (IS_ERR(ce->ceclks[i])) {
830 err = PTR_ERR(ce->ceclks[i]);
831 dev_err(ce->dev, "Cannot get %s CE clock err=%d\n",
832 ce->variant->ce_clks[i].name, err);
835 cr = clk_get_rate(ce->ceclks[i]);
838 if (ce->variant->ce_clks[i].freq > 0 &&
839 cr != ce->variant->ce_clks[i].freq) {
840 dev_info(ce->dev, "Set %s clock to %lu (%lu Mhz) from %lu (%lu Mhz)\n",
841 ce->variant->ce_clks[i].name,
842 ce->variant->ce_clks[i].freq,
843 ce->variant->ce_clks[i].freq / 1000000,
845 err = clk_set_rate(ce->ceclks[i], ce->variant->ce_clks[i].freq);
847 dev_err(ce->dev, "Fail to set %s clk speed to %lu hz\n",
848 ce->variant->ce_clks[i].name,
849 ce->variant->ce_clks[i].freq);
851 if (ce->variant->ce_clks[i].max_freq > 0 &&
852 cr > ce->variant->ce_clks[i].max_freq)
853 dev_warn(ce->dev, "Frequency for %s (%lu hz) is higher than datasheet's recommendation (%lu hz)",
854 ce->variant->ce_clks[i].name, cr,
855 ce->variant->ce_clks[i].max_freq);
860 static int sun8i_ce_register_algs(struct sun8i_ce_dev *ce)
866 ce_algs[i].ce = ce;
870 ce_method = ce->variant->alg_cipher[id];
872 dev_dbg(ce->dev,
875 ce_algs[i].ce = NULL;
879 ce_method = ce->variant->op_mode[id];
881 dev_dbg(ce->dev, "DEBUG: Blockmode of %s not supported\n",
883 ce_algs[i].ce = NULL;
886 dev_info(ce->dev, "Register %s\n",
890 dev_err(ce->dev, "ERROR: Fail to register %s\n",
892 ce_algs[i].ce = NULL;
898 ce_method = ce->variant->alg_hash[id];
900 dev_info(ce->dev,
903 ce_algs[i].ce = NULL;
906 dev_info(ce->dev, "Register %s\n",
910 dev_err(ce->dev, "ERROR: Fail to register %s\n",
912 ce_algs[i].ce = NULL;
917 if (ce->variant->prng == CE_ID_NOTSUPP) {
918 dev_info(ce->dev,
921 ce_algs[i].ce = NULL;
924 dev_info(ce->dev, "Register %s\n",
928 dev_err(ce->dev, "Fail to register %s\n",
930 ce_algs[i].ce = NULL;
934 ce_algs[i].ce = NULL;
935 dev_err(ce->dev, "ERROR: tried to register an unknown algo\n");
941 static void sun8i_ce_unregister_algs(struct sun8i_ce_dev *ce)
946 if (!ce_algs[i].ce)
950 dev_info(ce->dev, "Unregister %d %s\n", i,
955 dev_info(ce->dev, "Unregister %d %s\n", i,
960 dev_info(ce->dev, "Unregister %d %s\n", i,
970 struct sun8i_ce_dev *ce;
974 ce = devm_kzalloc(&pdev->dev, sizeof(*ce), GFP_KERNEL);
975 if (!ce)
978 ce->dev = &pdev->dev;
979 platform_set_drvdata(pdev, ce);
981 ce->variant = of_device_get_match_data(&pdev->dev);
982 if (!ce->variant) {
987 ce->base = devm_platform_ioremap_resource(pdev, 0);
988 if (IS_ERR(ce->base))
989 return PTR_ERR(ce->base);
991 err = sun8i_ce_get_clks(ce);
1000 ce->reset = devm_reset_control_get(&pdev->dev, NULL);
1001 if (IS_ERR(ce->reset))
1002 return dev_err_probe(&pdev->dev, PTR_ERR(ce->reset),
1005 mutex_init(&ce->mlock);
1006 mutex_init(&ce->rnglock);
1008 err = sun8i_ce_allocate_chanlist(ce);
1012 err = sun8i_ce_pm_init(ce);
1017 "sun8i-ce-ns", ce);
1019 dev_err(ce->dev, "Cannot request CryptoEngine Non-secure IRQ (err=%d)\n", err);
1023 err = sun8i_ce_register_algs(ce);
1027 err = pm_runtime_resume_and_get(ce->dev);
1032 sun8i_ce_hwrng_register(ce);
1035 v = readl(ce->base + CE_CTR);
1040 pm_runtime_put_sync(ce->dev);
1047 dbgfs_dir = debugfs_create_dir("sun8i-ce", NULL);
1049 dbgfs_dir, ce,
1053 ce->dbgfs_dir = dbgfs_dir;
1054 ce->dbgfs_stats = dbgfs_stats;
1060 sun8i_ce_unregister_algs(ce);
1062 sun8i_ce_pm_exit(ce);
1064 sun8i_ce_free_chanlist(ce, MAXFLOW - 1);
1070 struct sun8i_ce_dev *ce = platform_get_drvdata(pdev);
1073 sun8i_ce_hwrng_unregister(ce);
1076 sun8i_ce_unregister_algs(ce);
1079 debugfs_remove_recursive(ce->dbgfs_dir);
1082 sun8i_ce_free_chanlist(ce, MAXFLOW - 1);
1084 sun8i_ce_pm_exit(ce);
1108 .name = "sun8i-ce",