Lines Matching defs:flow
151 * The flow 3 is reserve for xRNG operations
155 return atomic_inc_return(&ce->flow) % (MAXFLOW - 1);
158 int sun8i_ce_run_task(struct sun8i_ce_dev *ce, int flow, const char *name)
162 struct ce_task *cet = ce->chanlist[flow].tl;
165 ce->chanlist[flow].stat_req++;
171 v |= 1 << flow;
174 reinit_completion(&ce->chanlist[flow].complete);
175 writel(ce->chanlist[flow].t_phy, ce->base + CE_TDQ);
177 ce->chanlist[flow].status = 0;
184 v = 1 | ((le32_to_cpu(ce->chanlist[flow].tl->t_common_ctl) & 0x7F) << 8);
188 wait_for_completion_interruptible_timeout(&ce->chanlist[flow].complete,
189 msecs_to_jiffies(ce->chanlist[flow].timeout));
191 if (ce->chanlist[flow].status == 0) {
192 dev_err(ce->dev, "DMA timeout for %s (tm=%d) on flow %d\n", name,
193 ce->chanlist[flow].timeout, flow);
202 /* Sadly, the error bit is not per flow */
204 dev_err(ce->dev, "CE ERROR: %x for flow %x\n", v, flow);
220 v >>= (flow * 4);
223 dev_err(ce->dev, "CE ERROR: %x for flow %x\n", v, flow);
236 v >>= (flow * 8);
239 dev_err(ce->dev, "CE ERROR: %x for flow %x\n", v, flow);
263 int flow = 0;
267 for (flow = 0; flow < MAXFLOW; flow++) {
268 if (p & (BIT(flow))) {
269 writel(BIT(flow), ce->base + CE_ISR);
270 ce->chanlist[flow].status = 1;
271 complete(&ce->chanlist[flow].complete);