comedi/drivers/rtd520.c

464 		writel(0, dev->mmio + LAS0_CGT_CLEAR);
465 		writel(1, dev->mmio + LAS0_CGT_ENABLE);
468 			       dev->mmio + LAS0_CGT_WRITE);
471 		writel(0, dev->mmio + LAS0_CGT_ENABLE);
473 		       dev->mmio + LAS0_CGL_WRITE);
488 	writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR);
491 	writel(0, dev->mmio + LAS0_ADC_CONVERSION);
496 		writew(0, dev->mmio + LAS0_ADC);
498 		fifo_status = readl(dev->mmio + LAS0_ADC);
508 	writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR);
525 	status = readl(dev->mmio + LAS0_ADC);
541 	writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR);
547 	writel(0, dev->mmio + LAS0_ADC_CONVERSION);
553 		writew(0, dev->mmio + LAS0_ADC);
620 	fifo_status = readl(dev->mmio + LAS0_ADC);
625 	status = readw(dev->mmio + LAS0_IT);
656 	overrun = readl(dev->mmio + LAS0_OVERRUN) & 0xffff;
661 	writew(status, dev->mmio + LAS0_CLEAR);
662 	readw(dev->mmio + LAS0_CLEAR);
675 	status = readw(dev->mmio + LAS0_IT);
676 	writew(status, dev->mmio + LAS0_CLEAR);
677 	readw(dev->mmio + LAS0_CLEAR);
679 	fifo_status = readl(dev->mmio + LAS0_ADC);
680 	overrun = readl(dev->mmio + LAS0_OVERRUN) & 0xffff;
836 	writel(0, dev->mmio + LAS0_PACER_STOP);
837 	writel(0, dev->mmio + LAS0_PACER);	/* stop pacer */
838 	writel(0, dev->mmio + LAS0_ADC_CONVERSION);
839 	writew(0, dev->mmio + LAS0_IT);
840 	writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR);
841 	writel(0, dev->mmio + LAS0_OVERRUN);
850 		writel(0, dev->mmio + LAS0_PACER_START);
852 		writel(1, dev->mmio + LAS0_BURST_START);
854 		writel(2, dev->mmio + LAS0_ADC_CONVERSION);
857 		writel(0, dev->mmio + LAS0_PACER_START);
859 		writel(1, dev->mmio + LAS0_ADC_CONVERSION);
861 	writel((devpriv->fifosz / 2 - 1) & 0xffff, dev->mmio + LAS0_ACNT);
897 			       dev->mmio + LAS0_ACNT);
904 	writel(1, dev->mmio + LAS0_PACER_SELECT);
906 	writel(1, dev->mmio + LAS0_ACNT_STOP_ENABLE);
931 		writel(timer & 0xffffff, dev->mmio + LAS0_PCLK);
937 		writel(1, dev->mmio + LAS0_PACER_START);
949 			writel(timer & 0x3ff, dev->mmio + LAS0_BCLK);
956 		writel(2, dev->mmio + LAS0_BURST_START);
965 	writew(~0, dev->mmio + LAS0_CLEAR);
966 	readw(dev->mmio + LAS0_CLEAR);
970 	writew(IRQM_ADC_ABOUT_CNT, dev->mmio + LAS0_IT);
974 	readl(dev->mmio + LAS0_PACER);	/* start pacer */
983 	writel(0, dev->mmio + LAS0_PACER_STOP);
984 	writel(0, dev->mmio + LAS0_PACER);	/* stop pacer */
985 	writel(0, dev->mmio + LAS0_ADC_CONVERSION);
986 	writew(0, dev->mmio + LAS0_IT);
988 	writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR);
1001 	status = readl(dev->mmio + LAS0_ADC);
1019 	writew(range & 7, dev->mmio + LAS0_DAC_CTRL(chan));
1034 		writew(0, dev->mmio + LAS0_UPDATE_DAC(chan));
1052 		writew(s->state & 0xff, dev->mmio + LAS0_DIO0);
1054 	data[1] = readw(dev->mmio + LAS0_DIO0) & 0xff;
1073 	writew(0x01, dev->mmio + LAS0_DIO_STATUS);
1074 	writew(s->io_bits & 0xff, dev->mmio + LAS0_DIO0_CTRL);
1077 	writew(0x00, dev->mmio + LAS0_DIO_STATUS);
1113 		writeb(src, dev->mmio + LAS0_8254_GATE_SEL(chan));
1147 		writeb(src, dev->mmio + LAS0_8254_CLK_SEL(chan));
1165 	writel(0, dev->mmio + LAS0_BOARD_RESET);
1168 	writew(0, dev->mmio + LAS0_IT);
1169 	writew(~0, dev->mmio + LAS0_CLEAR);
1170 	readw(dev->mmio + LAS0_CLEAR);
1181 	writel(0, dev->mmio + LAS0_OVERRUN);
1182 	writel(0, dev->mmio + LAS0_CGT_CLEAR);
1183 	writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR);
1184 	writel(0, dev->mmio + LAS0_DAC_RESET(0));
1185 	writel(0, dev->mmio + LAS0_DAC_RESET(1));
1187 	writew(0, dev->mmio + LAS0_DIO_STATUS);
1230 	dev->mmio = pci_ioremap_bar(pcidev, 2);
1233 	if (!dev->mmio || !devpriv->las1 || !devpriv->lcfg)
1292 	dev->pacer = comedi_8254_mm_alloc(dev->mmio + LAS0_8254_TIMER_BASE,
1320 		if (dev->mmio && devpriv->lcfg)
1324 		if (dev->mmio)
1325 			iounmap(dev->mmio);