comedi/drivers/ni_pcidio.c

311 	       dev->mmio + DMA_LINE_CONTROL_GROUP1);
327 		       dev->mmio + DMA_LINE_CONTROL_GROUP1);
393 	status = readb(dev->mmio + INTERRUPT_AND_WINDOW_STATUS);
394 	flags = readb(dev->mmio + GROUP_1_FLAGS);
408 			       dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL);
420 					writeb(0x00, dev->mmio +
425 				auxdata = readl(dev->mmio + GROUP_1_FIFO);
427 				flags = readb(dev->mmio + GROUP_1_FLAGS);
432 			writeb(CLEAR_EXPIRED, dev->mmio + GROUP_1_SECOND_CLEAR);
435 			writeb(0x00, dev->mmio + OP_MODE);
438 			writeb(CLEAR_WAITED, dev->mmio + GROUP_1_FIRST_CLEAR);
443 			       dev->mmio + GROUP_1_FIRST_CLEAR);
447 			       dev->mmio + GROUP_1_FIRST_CLEAR);
451 		flags = readb(dev->mmio + GROUP_1_FLAGS);
452 		status = readb(dev->mmio + INTERRUPT_AND_WINDOW_STATUS);
459 		writeb(0x03, dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL);
486 	writel(s->io_bits, dev->mmio + PORT_PIN_DIRECTIONS(0));
497 		writel(s->state, dev->mmio + PORT_IO(0));
499 	data[1] = readl(dev->mmio + PORT_IO(0));
611 	writeb(devpriv->OP_MODEBits, dev->mmio + OP_MODE);
623 	writel(0x0000, dev->mmio + PORT_PIN_DIRECTIONS(0));
627 		writeb(0x0f, dev->mmio + DATA_PATH);
631 		       dev->mmio + TRANSFER_SIZE_CONTROL);
633 		writeb(0x03, dev->mmio + DATA_PATH);
635 		       dev->mmio + TRANSFER_SIZE_CONTROL);
641 		writeb(0, dev->mmio + OP_MODE);
642 		writeb(0x00, dev->mmio + CLOCK_REG);
643 		writeb(1, dev->mmio + SEQUENCE);
644 		writeb(0x04, dev->mmio + REQ_REG);
645 		writeb(4, dev->mmio + BLOCK_MODE);
646 		writeb(3, dev->mmio + LINE_POLARITIES);
647 		writeb(0xc0, dev->mmio + ACK_SER);
650 		       dev->mmio + START_DELAY);
651 		writeb(1, dev->mmio + REQ_DELAY);
652 		writeb(1, dev->mmio + REQ_NOT_DELAY);
653 		writeb(1, dev->mmio + ACK_DELAY);
654 		writeb(0x0b, dev->mmio + ACK_NOT_DELAY);
655 		writeb(0x01, dev->mmio + DATA_1_DELAY);
660 		writew(0, dev->mmio + CLOCK_SPEED);
661 		writeb(0, dev->mmio + DAQ_OPTIONS);
665 		writeb(0, dev->mmio + OP_MODE);
666 		writeb(0x00, dev->mmio + CLOCK_REG);
667 		writeb(0, dev->mmio + SEQUENCE);
668 		writeb(0x00, dev->mmio + REQ_REG);
669 		writeb(4, dev->mmio + BLOCK_MODE);
671 			writeb(0, dev->mmio + LINE_POLARITIES);
673 			writeb(2, dev->mmio + LINE_POLARITIES);
674 		writeb(0x00, dev->mmio + ACK_SER);
675 		writel(1, dev->mmio + START_DELAY);
676 		writeb(1, dev->mmio + REQ_DELAY);
677 		writeb(1, dev->mmio + REQ_NOT_DELAY);
678 		writeb(1, dev->mmio + ACK_DELAY);
679 		writeb(0x0C, dev->mmio + ACK_NOT_DELAY);
680 		writeb(0x10, dev->mmio + DATA_1_DELAY);
681 		writew(0, dev->mmio + CLOCK_SPEED);
682 		writeb(0x60, dev->mmio + DAQ_OPTIONS);
687 		       dev->mmio + TRANSFER_COUNT);
694 	       dev->mmio + GROUP_1_FIRST_CLEAR);
703 	writeb(0x00, dev->mmio + DMA_LINE_CONTROL_GROUP1);
705 	writeb(0x00, dev->mmio + DMA_LINE_CONTROL_GROUP2);
708 	writeb(0xff, dev->mmio + GROUP_1_FIRST_CLEAR);
709 	/* writeb(CLEAR_EXPIRED, dev->mmio+GROUP_1_SECOND_CLEAR); */
711 	writeb(INT_EN, dev->mmio + INTERRUPT_CONTROL);
712 	writeb(0x03, dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL);
721 		writeb(devpriv->OP_MODEBits, dev->mmio + OP_MODE);
734 	writeb(0x00, dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL);
764 	writew(0x80 | fpga_index, dev->mmio + Firmware_Control_Register);
765 	writew(0xc0 | fpga_index, dev->mmio + Firmware_Control_Register);
767 	     (readw(dev->mmio + Firmware_Status_Register) & 0x2) == 0 &&
777 	writew(0x80 | fpga_index, dev->mmio + Firmware_Control_Register);
779 	     readw(dev->mmio + Firmware_Status_Register) != 0x3 &&
793 		writew(value, dev->mmio + Firmware_Data_Register);
795 		     (readw(dev->mmio + Firmware_Status_Register) & 0x2) == 0
808 	writew(0x0, dev->mmio + Firmware_Control_Register);
822 	writew(0x0, dev->mmio + Firmware_Control_Register);
828 	writew(0x0, dev->mmio + Firmware_Mask_Register);
834 	writel(0, dev->mmio + FPGA_Control1_Register);
835 	writel(0, dev->mmio + FPGA_Control2_Register);
836 	writel(0, dev->mmio + FPGA_SCALS_Counter_Register);
837 	writel(0, dev->mmio + FPGA_SCAMS_Counter_Register);
838 	writel(0, dev->mmio + FPGA_SCBLS_Counter_Register);
839 	writel(0, dev->mmio + FPGA_SCBMS_Counter_Register);
871 	writel(0, dev->mmio + PORT_IO(0));
872 	writel(0, dev->mmio + PORT_PIN_DIRECTIONS(0));
873 	writel(0, dev->mmio + PORT_PIN_MASK(0));
876 	writeb(0, dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL);
927 		 readb(dev->mmio + CHIP_VERSION));
973 	if (dev->mmio)
974 		iounmap(dev->mmio);