Lines Matching refs:mmio
89 writeb(val & 0xff, dev->mmio + NI6527_FILT_INTERVAL_REG(0));
91 dev->mmio + NI6527_FILT_INTERVAL_REG(1));
93 dev->mmio + NI6527_FILT_INTERVAL_REG(2));
95 writeb(NI6527_CLR_INTERVAL, dev->mmio + NI6527_CLR_REG);
104 writeb(val & 0xff, dev->mmio + NI6527_FILT_ENA_REG(0));
105 writeb((val >> 8) & 0xff, dev->mmio + NI6527_FILT_ENA_REG(1));
106 writeb((val >> 16) & 0xff, dev->mmio + NI6527_FILT_ENA_REG(2));
150 val = readb(dev->mmio + NI6527_DI_REG(0));
151 val |= (readb(dev->mmio + NI6527_DI_REG(1)) << 8);
152 val |= (readb(dev->mmio + NI6527_DI_REG(2)) << 16);
172 writeb(val & 0xff, dev->mmio + NI6527_DO_REG(0));
175 dev->mmio + NI6527_DO_REG(1));
178 dev->mmio + NI6527_DO_REG(2));
192 status = readb(dev->mmio + NI6527_STATUS_REG);
203 writeb(NI6527_CLR_IRQS, dev->mmio + NI6527_CLR_REG);
250 writeb(NI6527_CLR_IRQS, dev->mmio + NI6527_CLR_REG);
251 writeb(NI6527_CTRL_ENABLE_IRQS, dev->mmio + NI6527_CTRL_REG);
259 writeb(NI6527_CTRL_DISABLE_IRQS, dev->mmio + NI6527_CTRL_REG);
285 rising |= readb(dev->mmio +
289 falling |= readb(dev->mmio +
295 dev->mmio + NI6527_RISING_EDGE_REG(i));
298 dev->mmio + NI6527_FALLING_EDGE_REG(i));
367 dev->mmio + NI6527_CLR_REG);
368 writeb(NI6527_CTRL_DISABLE_IRQS, dev->mmio + NI6527_CTRL_REG);
395 dev->mmio = pci_ioremap_bar(pcidev, 1);
396 if (!dev->mmio)
400 if (readb(dev->mmio + NI6527_ID_REG) != 0x27)
457 if (dev->mmio)