drivers/clocksource/timer-mediatek.c

56 #define SYST_CON_REG(to)        (timer_of_base(to) + SYST_CON)
57 #define SYST_VAL_REG(to)        (timer_of_base(to) + SYST_VAL)
60  * SYST_CON_EN: Clock enable. Shall be set to
65  * SYST_CON_IRQ_EN: Set to enable interrupt.
67  * SYST_CON_IRQ_CLR: Set to clear interrupt.
75 static void mtk_syst_ack_irq(struct timer_of *to)
78 	writel(SYST_CON_EN, SYST_CON_REG(to));
79 	writel(SYST_CON_IRQ_CLR | SYST_CON_EN, SYST_CON_REG(to));
85 	struct timer_of *to = to_timer_of(clkevt);
87 	mtk_syst_ack_irq(to);
96 	struct timer_of *to = to_timer_of(clkevt);
98 	/* Enable clock to allow timeout tick update later */
99 	writel(SYST_CON_EN, SYST_CON_REG(to));
105 	writel(ticks, SYST_VAL_REG(to));
108 	writel(SYST_CON_EN | SYST_CON_IRQ_EN, SYST_CON_REG(to));
139 static void mtk_gpt_clkevt_time_stop(struct timer_of *to, u8 timer)
143 	val = readl(timer_of_base(to) + GPT_CTRL_REG(timer));
144 	writel(val & ~GPT_CTRL_ENABLE, timer_of_base(to) +
148 static void mtk_gpt_clkevt_time_setup(struct timer_of *to,
151 	writel(delay, timer_of_base(to) + GPT_CMP_REG(timer));
154 static void mtk_gpt_clkevt_time_start(struct timer_of *to,
160 	writel(GPT_IRQ_ACK(timer), timer_of_base(to) + GPT_IRQ_ACK_REG);
162 	val = readl(timer_of_base(to) + GPT_CTRL_REG(timer));
173 	       timer_of_base(to) + GPT_CTRL_REG(timer));
185 	struct timer_of *to = to_timer_of(clk);
187 	mtk_gpt_clkevt_time_stop(to, TIMER_CLK_EVT);
188 	mtk_gpt_clkevt_time_setup(to, to->of_clk.period, TIMER_CLK_EVT);
189 	mtk_gpt_clkevt_time_start(to, true, TIMER_CLK_EVT);
197 	struct timer_of *to = to_timer_of(clk);
199 	mtk_gpt_clkevt_time_stop(to, TIMER_CLK_EVT);
200 	mtk_gpt_clkevt_time_setup(to, event, TIMER_CLK_EVT);
201 	mtk_gpt_clkevt_time_start(to, false, TIMER_CLK_EVT);
209 	struct timer_of *to = to_timer_of(clkevt);
212 	writel(GPT_IRQ_ACK(TIMER_CLK_EVT), timer_of_base(to) + GPT_IRQ_ACK_REG);
219 __init mtk_gpt_setup(struct timer_of *to, u8 timer, u8 option)
222 	       timer_of_base(to) + GPT_CTRL_REG(timer));
225 	       timer_of_base(to) + GPT_CLK_REG(timer));
227 	writel(0x0, timer_of_base(to) + GPT_CMP_REG(timer));
230 	       timer_of_base(to) + GPT_CTRL_REG(timer));
233 static void mtk_gpt_enable_irq(struct timer_of *to, u8 timer)
238 	writel(0x0, timer_of_base(to) + GPT_IRQ_EN_REG);
241 	writel(0x3f, timer_of_base(to) + GPT_IRQ_ACK_REG);
243 	val = readl(timer_of_base(to) + GPT_IRQ_EN_REG);
245 	       timer_of_base(to) + GPT_IRQ_EN_REG);
250 	struct timer_of *to = to_timer_of(clk);
252 	mtk_gpt_enable_irq(to, TIMER_CLK_EVT);
257 	struct timer_of *to = to_timer_of(clk);
260 	writel(0x0, timer_of_base(to) + GPT_IRQ_EN_REG);
264 	 * so we need to ack any interrupt that is pending
267 	writel(0x3f, timer_of_base(to) + GPT_IRQ_ACK_REG);
270 static struct timer_of to = {
288 	to.clkevt.features = CLOCK_EVT_FEAT_DYNIRQ | CLOCK_EVT_FEAT_ONESHOT;
289 	to.clkevt.set_state_shutdown = mtk_syst_clkevt_shutdown;
290 	to.clkevt.set_state_oneshot = mtk_syst_clkevt_oneshot;
291 	to.clkevt.tick_resume = mtk_syst_clkevt_resume;
292 	to.clkevt.set_next_event = mtk_syst_clkevt_next_event;
293 	to.of_irq.handler = mtk_syst_handler;
295 	ret = timer_of_init(node, &to);
299 	clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),
309 	to.clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
310 	to.clkevt.set_state_shutdown = mtk_gpt_clkevt_shutdown;
311 	to.clkevt.set_state_periodic = mtk_gpt_clkevt_set_periodic;
312 	to.clkevt.set_state_oneshot = mtk_gpt_clkevt_shutdown;
313 	to.clkevt.tick_resume = mtk_gpt_clkevt_shutdown;
314 	to.clkevt.set_next_event = mtk_gpt_clkevt_next_event;
315 	to.clkevt.suspend = mtk_gpt_suspend;
316 	to.clkevt.resume = mtk_gpt_resume;
317 	to.of_irq.handler = mtk_gpt_interrupt;
319 	ret = timer_of_init(node, &to);
324 	mtk_gpt_setup(&to, TIMER_CLK_SRC, GPT_CTRL_OP_FREERUN);
325 	clocksource_mmio_init(timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC),
326 			      node->name, timer_of_rate(&to), 300, 32,
328 	gpt_sched_reg = timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC);
329 	sched_clock_register(mtk_gpt_read_sched_clock, 32, timer_of_rate(&to));
332 	mtk_gpt_setup(&to, TIMER_CLK_EVT, GPT_CTRL_OP_REPEAT);
333 	clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),
336 	mtk_gpt_enable_irq(&to, TIMER_CLK_EVT);