drivers/clocksource/timer-ixp4xx.c

84 	struct ixp4xx_timer *tmr = dev_id;
85 	struct clock_event_device *evt = &tmr->clkevt;
89 		     tmr->base + IXP4XX_OSST_OFFSET);
99 	struct ixp4xx_timer *tmr = to_ixp4xx_timer(evt);
102 	val = __raw_readl(tmr->base + IXP4XX_OSRT1_OFFSET);
106 		     tmr->base + IXP4XX_OSRT1_OFFSET);
113 	struct ixp4xx_timer *tmr = to_ixp4xx_timer(evt);
116 	val = __raw_readl(tmr->base + IXP4XX_OSRT1_OFFSET);
118 	__raw_writel(val, tmr->base + IXP4XX_OSRT1_OFFSET);
125 	struct ixp4xx_timer *tmr = to_ixp4xx_timer(evt);
128 		     tmr->base + IXP4XX_OSRT1_OFFSET);
135 	struct ixp4xx_timer *tmr = to_ixp4xx_timer(evt);
138 	val = tmr->latch & ~IXP4XX_OST_RELOAD_MASK;
140 	__raw_writel(val, tmr->base + IXP4XX_OSRT1_OFFSET);
147 	struct ixp4xx_timer *tmr = to_ixp4xx_timer(evt);
150 	val = __raw_readl(tmr->base + IXP4XX_OSRT1_OFFSET);
152 	__raw_writel(val, tmr->base + IXP4XX_OSRT1_OFFSET);
166 	struct ixp4xx_timer *tmr;
169 	tmr = kzalloc(sizeof(*tmr), GFP_KERNEL);
170 	if (!tmr)
172 	tmr->base = base;
180 	tmr->latch = DIV_ROUND_CLOSEST(timer_freq,
184 	local_ixp4xx_timer = tmr;
187 	__raw_writel(0, tmr->base + IXP4XX_OSRT1_OFFSET);
191 		     tmr->base + IXP4XX_OSST_OFFSET);
194 	__raw_writel(0, tmr->base + IXP4XX_OSTS_OFFSET);
199 	tmr->clkevt.name = "ixp4xx timer1";
200 	tmr->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
201 	tmr->clkevt.rating = 200;
202 	tmr->clkevt.set_state_shutdown = ixp4xx_shutdown;
203 	tmr->clkevt.set_state_periodic = ixp4xx_set_periodic;
204 	tmr->clkevt.set_state_oneshot = ixp4xx_set_oneshot;
205 	tmr->clkevt.tick_resume = ixp4xx_resume;
206 	tmr->clkevt.set_next_event = ixp4xx_set_next_event;
207 	tmr->clkevt.cpumask = cpumask_of(0);
208 	tmr->clkevt.irq = timer_irq;
210 			  IRQF_TIMER, "IXP4XX-TIMER1", tmr);
215 	clockevents_config_and_register(&tmr->clkevt, timer_freq,
222 	tmr->delay_timer.read_current_timer = ixp4xx_read_timer;
223 	tmr->delay_timer.freq = timer_freq;
224 	register_current_timer_delay(&tmr->delay_timer);