Lines Matching refs:base_addr
69 * @base_addr: Base address of timer
75 void __iomem *base_addr;
116 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
118 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
120 writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);
128 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
145 readl_relaxed(timer->base_addr + TTC_ISR_OFFSET);
162 return (u64)readl_relaxed(timer->base_addr +
203 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
205 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
231 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
233 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
276 readl_relaxed(ttccs->ttc.base_addr +
302 ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
312 ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
322 ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
360 ttccs->ttc.base_addr = base;
372 writel_relaxed(0x0, ttccs->ttc.base_addr + TTC_IER_OFFSET);
374 ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
376 ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
443 ttcce->ttc.base_addr = base;
460 writel_relaxed(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
462 ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
463 writel_relaxed(0x1, ttcce->ttc.base_addr + TTC_IER_OFFSET);