Lines Matching refs:ch
241 static inline u32 sh_cmt_read_cmstr(struct sh_cmt_channel *ch)
243 if (ch->iostart)
244 return ch->cmt->info->read_control(ch->iostart, 0);
246 return ch->cmt->info->read_control(ch->cmt->mapbase, 0);
249 static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch, u32 value)
251 u32 old_value = sh_cmt_read_cmstr(ch);
254 if (ch->iostart) {
255 ch->cmt->info->write_control(ch->iostart, 0, value);
256 udelay(ch->cmt->reg_delay);
258 ch->cmt->info->write_control(ch->cmt->mapbase, 0, value);
259 udelay(ch->cmt->reg_delay);
264 static inline u32 sh_cmt_read_cmcsr(struct sh_cmt_channel *ch)
266 return ch->cmt->info->read_control(ch->ioctrl, CMCSR);
269 static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch, u32 value)
271 u32 old_value = sh_cmt_read_cmcsr(ch);
274 ch->cmt->info->write_control(ch->ioctrl, CMCSR, value);
275 udelay(ch->cmt->reg_delay);
279 static inline u32 sh_cmt_read_cmcnt(struct sh_cmt_channel *ch)
281 return ch->cmt->info->read_count(ch->ioctrl, CMCNT);
284 static inline int sh_cmt_write_cmcnt(struct sh_cmt_channel *ch, u32 value)
287 unsigned int cmcnt_delay = DIV_ROUND_UP(3 * ch->cmt->reg_delay, 2);
290 if (ch->cmt->info->model > SH_CMT_16BIT) {
293 1, cmcnt_delay, false, ch);
298 ch->cmt->info->write_count(ch->ioctrl, CMCNT, value);
303 static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch, u32 value)
305 u32 old_value = ch->cmt->info->read_count(ch->ioctrl, CMCOR);
308 ch->cmt->info->write_count(ch->ioctrl, CMCOR, value);
309 udelay(ch->cmt->reg_delay);
313 static u32 sh_cmt_get_counter(struct sh_cmt_channel *ch, u32 *has_wrapped)
318 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
323 v1 = sh_cmt_read_cmcnt(ch);
324 v2 = sh_cmt_read_cmcnt(ch);
325 v3 = sh_cmt_read_cmcnt(ch);
326 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
334 static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start)
340 raw_spin_lock_irqsave(&ch->cmt->lock, flags);
341 value = sh_cmt_read_cmstr(ch);
344 value |= 1 << ch->timer_bit;
346 value &= ~(1 << ch->timer_bit);
348 sh_cmt_write_cmstr(ch, value);
349 raw_spin_unlock_irqrestore(&ch->cmt->lock, flags);
352 static int sh_cmt_enable(struct sh_cmt_channel *ch)
356 dev_pm_syscore_device(&ch->cmt->pdev->dev, true);
359 ret = clk_enable(ch->cmt->clk);
361 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n",
362 ch->index);
367 sh_cmt_start_stop_ch(ch, 0);
370 if (ch->cmt->info->width == 16) {
371 sh_cmt_write_cmcsr(ch, SH_CMT16_CMCSR_CMIE |
374 u32 cmtout = ch->cmt->info->model <= SH_CMT_48BIT ?
376 sh_cmt_write_cmcsr(ch, cmtout | SH_CMT32_CMCSR_CMM |
381 sh_cmt_write_cmcor(ch, 0xffffffff);
382 ret = sh_cmt_write_cmcnt(ch, 0);
384 if (ret || sh_cmt_read_cmcnt(ch)) {
385 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n",
386 ch->index);
392 sh_cmt_start_stop_ch(ch, 1);
396 clk_disable(ch->cmt->clk);
402 static void sh_cmt_disable(struct sh_cmt_channel *ch)
405 sh_cmt_start_stop_ch(ch, 0);
408 sh_cmt_write_cmcsr(ch, 0);
411 clk_disable(ch->cmt->clk);
413 dev_pm_syscore_device(&ch->cmt->pdev->dev, false);
423 static void sh_cmt_clock_event_program_verify(struct sh_cmt_channel *ch,
426 u32 value = ch->next_match_value;
432 now = sh_cmt_get_counter(ch, &has_wrapped);
433 ch->flags |= FLAG_REPROGRAM; /* force reprogram */
440 ch->flags |= FLAG_SKIPEVENT;
452 if (new_match > ch->max_match_value)
453 new_match = ch->max_match_value;
455 sh_cmt_write_cmcor(ch, new_match);
457 now = sh_cmt_get_counter(ch, &has_wrapped);
458 if (has_wrapped && (new_match > ch->match_value)) {
465 ch->flags |= FLAG_SKIPEVENT;
476 ch->match_value = new_match;
487 ch->match_value = new_match;
503 dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n",
504 ch->index);
509 static void __sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta)
511 if (delta > ch->max_match_value)
512 dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n",
513 ch->index);
515 ch->next_match_value = delta;
516 sh_cmt_clock_event_program_verify(ch, 0);
519 static void sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta)
523 raw_spin_lock_irqsave(&ch->lock, flags);
524 __sh_cmt_set_next(ch, delta);
525 raw_spin_unlock_irqrestore(&ch->lock, flags);
530 struct sh_cmt_channel *ch = dev_id;
533 sh_cmt_write_cmcsr(ch, sh_cmt_read_cmcsr(ch) &
534 ch->cmt->info->clear_bits);
540 if (ch->flags & FLAG_CLOCKSOURCE)
541 ch->total_cycles += ch->match_value + 1;
543 if (!(ch->flags & FLAG_REPROGRAM))
544 ch->next_match_value = ch->max_match_value;
546 ch->flags |= FLAG_IRQCONTEXT;
548 if (ch->flags & FLAG_CLOCKEVENT) {
549 if (!(ch->flags & FLAG_SKIPEVENT)) {
550 if (clockevent_state_oneshot(&ch->ced)) {
551 ch->next_match_value = ch->max_match_value;
552 ch->flags |= FLAG_REPROGRAM;
555 ch->ced.event_handler(&ch->ced);
559 ch->flags &= ~FLAG_SKIPEVENT;
561 if (ch->flags & FLAG_REPROGRAM) {
562 ch->flags &= ~FLAG_REPROGRAM;
563 sh_cmt_clock_event_program_verify(ch, 1);
565 if (ch->flags & FLAG_CLOCKEVENT)
566 if ((clockevent_state_shutdown(&ch->ced))
567 || (ch->match_value == ch->next_match_value))
568 ch->flags &= ~FLAG_REPROGRAM;
571 ch->flags &= ~FLAG_IRQCONTEXT;
576 static int sh_cmt_start(struct sh_cmt_channel *ch, unsigned long flag)
582 pm_runtime_get_sync(&ch->cmt->pdev->dev);
584 raw_spin_lock_irqsave(&ch->lock, flags);
586 if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) {
588 pm_runtime_get_sync(&ch->cmt->pdev->dev);
589 ret = sh_cmt_enable(ch);
594 ch->flags |= flag;
597 if (ch->cmt->num_channels == 1 &&
598 flag == FLAG_CLOCKSOURCE && (!(ch->flags & FLAG_CLOCKEVENT)))
599 __sh_cmt_set_next(ch, ch->max_match_value);
601 raw_spin_unlock_irqrestore(&ch->lock, flags);
606 static void sh_cmt_stop(struct sh_cmt_channel *ch, unsigned long flag)
611 raw_spin_lock_irqsave(&ch->lock, flags);
613 f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE);
614 ch->flags &= ~flag;
616 if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) {
617 sh_cmt_disable(ch);
619 pm_runtime_put(&ch->cmt->pdev->dev);
623 if ((flag == FLAG_CLOCKEVENT) && (ch->flags & FLAG_CLOCKSOURCE))
624 __sh_cmt_set_next(ch, ch->max_match_value);
626 raw_spin_unlock_irqrestore(&ch->lock, flags);
629 pm_runtime_put(&ch->cmt->pdev->dev);
639 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
642 if (ch->cmt->num_channels == 1) {
647 raw_spin_lock_irqsave(&ch->lock, flags);
648 value = ch->total_cycles;
649 raw = sh_cmt_get_counter(ch, &has_wrapped);
652 raw += ch->match_value + 1;
653 raw_spin_unlock_irqrestore(&ch->lock, flags);
658 return sh_cmt_get_counter(ch, &has_wrapped);
664 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
666 WARN_ON(ch->cs_enabled);
668 ch->total_cycles = 0;
670 ret = sh_cmt_start(ch, FLAG_CLOCKSOURCE);
672 ch->cs_enabled = true;
679 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
681 WARN_ON(!ch->cs_enabled);
683 sh_cmt_stop(ch, FLAG_CLOCKSOURCE);
684 ch->cs_enabled = false;
689 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
691 if (!ch->cs_enabled)
694 sh_cmt_stop(ch, FLAG_CLOCKSOURCE);
695 dev_pm_genpd_suspend(&ch->cmt->pdev->dev);
700 struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
702 if (!ch->cs_enabled)
705 dev_pm_genpd_resume(&ch->cmt->pdev->dev);
706 sh_cmt_start(ch, FLAG_CLOCKSOURCE);
709 static int sh_cmt_register_clocksource(struct sh_cmt_channel *ch,
712 struct clocksource *cs = &ch->cs;
721 cs->mask = CLOCKSOURCE_MASK(ch->cmt->info->width);
724 dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n",
725 ch->index);
727 clocksource_register_hz(cs, ch->cmt->rate);
736 static void sh_cmt_clock_event_start(struct sh_cmt_channel *ch, int periodic)
738 sh_cmt_start(ch, FLAG_CLOCKEVENT);
741 sh_cmt_set_next(ch, ((ch->cmt->rate + HZ/2) / HZ) - 1);
743 sh_cmt_set_next(ch, ch->max_match_value);
748 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
750 sh_cmt_stop(ch, FLAG_CLOCKEVENT);
757 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
761 sh_cmt_stop(ch, FLAG_CLOCKEVENT);
763 dev_info(&ch->cmt->pdev->dev, "ch%u: used for %s clock events\n",
764 ch->index, periodic ? "periodic" : "oneshot");
765 sh_cmt_clock_event_start(ch, periodic);
782 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
785 if (likely(ch->flags & FLAG_IRQCONTEXT))
786 ch->next_match_value = delta - 1;
788 sh_cmt_set_next(ch, delta - 1);
795 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
797 dev_pm_genpd_suspend(&ch->cmt->pdev->dev);
798 clk_unprepare(ch->cmt->clk);
803 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
805 clk_prepare(ch->cmt->clk);
806 dev_pm_genpd_resume(&ch->cmt->pdev->dev);
809 static int sh_cmt_register_clockevent(struct sh_cmt_channel *ch,
812 struct clock_event_device *ced = &ch->ced;
816 irq = platform_get_irq(ch->cmt->pdev, ch->index);
822 dev_name(&ch->cmt->pdev->dev), ch);
824 dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n",
825 ch->index, irq);
843 ced->mult = div_sc(ch->cmt->rate, NSEC_PER_SEC, ced->shift);
844 ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced);
845 ced->max_delta_ticks = ch->max_match_value;
849 dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n",
850 ch->index);
856 static int sh_cmt_register(struct sh_cmt_channel *ch, const char *name,
862 ch->cmt->has_clockevent = true;
863 ret = sh_cmt_register_clockevent(ch, name);
869 ch->cmt->has_clocksource = true;
870 sh_cmt_register_clocksource(ch, name);
876 static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index,
887 ch->cmt = cmt;
888 ch->index = index;
889 ch->hwidx = hwidx;
890 ch->timer_bit = hwidx;
899 ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6;
903 ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10;
907 ch->iostart = cmt->mapbase + ch->hwidx * 0x100;
908 ch->ioctrl = ch->iostart + 0x10;
909 ch->timer_bit = 0;
918 if (cmt->info->width == (sizeof(ch->max_match_value) * 8))
919 ch->max_match_value = ~0;
921 ch->max_match_value = (1 << cmt->info->width) - 1;
923 ch->match_value = ch->max_match_value;
924 raw_spin_lock_init(&ch->lock);
926 ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev),
929 dev_err(&cmt->pdev->dev, "ch%u: registration failed\n",
930 ch->index);
933 ch->cs_enabled = false;