drivers/clocksource/samsung_pwm_timer.c

79 static struct samsung_pwm_clocksource pwm;
92 	reg = readl(pwm.base + REG_TCFG0);
95 	writel(reg, pwm.base + REG_TCFG0);
107 	bits = (fls(divisor) - 1) - pwm.variant.div_base;
111 	reg = readl(pwm.base + REG_TCFG1);
114 	writel(reg, pwm.base + REG_TCFG1);
129 	tcon = readl_relaxed(pwm.base + REG_TCON);
131 	writel_relaxed(tcon, pwm.base + REG_TCON);
147 	tcon = readl_relaxed(pwm.base + REG_TCON);
152 	writel_relaxed(tcnt, pwm.base + REG_TCNTB(channel));
153 	writel_relaxed(tcnt, pwm.base + REG_TCMPB(channel));
154 	writel_relaxed(tcon, pwm.base + REG_TCON);
169 	tcon = readl_relaxed(pwm.base + REG_TCON);
179 	writel_relaxed(tcon, pwm.base + REG_TCON);
200 	samsung_time_setup(pwm.event_id, cycles);
201 	samsung_time_start(pwm.event_id, false);
208 	samsung_time_stop(pwm.event_id);
214 	samsung_time_stop(pwm.event_id);
215 	samsung_time_setup(pwm.event_id, pwm.clock_count_per_tick - 1);
216 	samsung_time_start(pwm.event_id, true);
222 	samsung_timer_set_prescale(pwm.event_id, pwm.tscaler_div);
223 	samsung_timer_set_divisor(pwm.event_id, pwm.tdiv);
225 	if (pwm.variant.has_tint_cstat) {
226 		u32 mask = (1 << pwm.event_id);
228 		writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT);
249 	if (pwm.variant.has_tint_cstat) {
250 		u32 mask = (1 << pwm.event_id);
252 		writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT);
266 	pclk = clk_get_rate(pwm.timerclk);
268 	samsung_timer_set_prescale(pwm.event_id, pwm.tscaler_div);
269 	samsung_timer_set_divisor(pwm.event_id, pwm.tdiv);
271 	clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv);
272 	pwm.clock_count_per_tick = clock_rate / HZ;
276 					clock_rate, 1, pwm.tcnt_max);
278 	irq_number = pwm.irq[pwm.event_id];
284 	if (pwm.variant.has_tint_cstat) {
285 		u32 mask = (1 << pwm.event_id);
287 		writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT);
293 	samsung_time_stop(pwm.source_id);
298 	samsung_timer_set_prescale(pwm.source_id, pwm.tscaler_div);
299 	samsung_timer_set_divisor(pwm.source_id, pwm.tdiv);
301 	samsung_time_setup(pwm.source_id, pwm.tcnt_max);
302 	samsung_time_start(pwm.source_id, true);
307 	return ~readl_relaxed(pwm.source_reg);
336 	pclk = clk_get_rate(pwm.timerclk);
338 	samsung_timer_set_prescale(pwm.source_id, pwm.tscaler_div);
339 	samsung_timer_set_divisor(pwm.source_id, pwm.tdiv);
341 	clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv);
343 	samsung_time_setup(pwm.source_id, pwm.tcnt_max);
344 	samsung_time_start(pwm.source_id, true);
346 	if (pwm.source_id == 4)
347 		pwm.source_reg = pwm.base + 0x40;
349 		pwm.source_reg = pwm.base + pwm.source_id * 0x0c + 0x14;
352 			     pwm.variant.bits, clock_rate);
354 	samsung_clocksource.mask = CLOCKSOURCE_MASK(pwm.variant.bits);
360 	clk_prepare_enable(pwm.timerclk);
362 	pwm.tcnt_max = (1UL << pwm.variant.bits) - 1;
363 	if (pwm.variant.bits == 16) {
364 		pwm.tscaler_div = 25;
365 		pwm.tdiv = 2;
367 		pwm.tscaler_div = 2;
368 		pwm.tdiv = 1;
380 	mask = ~pwm.variant.output_mask & ((1 << SAMSUNG_PWM_NUM) - 1);
386 	pwm.source_id = channel;
394 	pwm.event_id = channel;
406 	pwm.base = base;
407 	memcpy(&pwm.variant, variant, sizeof(pwm.variant));
408 	memcpy(pwm.irq, irqs, SAMSUNG_PWM_NUM * sizeof(*irqs));
410 	pwm.timerclk = clk_get(NULL, "timers");
411 	if (IS_ERR(pwm.timerclk))
426 	memcpy(&pwm.variant, variant, sizeof(pwm.variant));
428 		pwm.irq[i] = irq_of_parse_and_map(np, i);
430 	of_property_for_each_u32(np, "samsung,pwm-outputs", prop, cur, val) {
432 			pr_warn("%s: invalid channel index in samsung,pwm-outputs property\n", __func__);
435 		pwm.variant.output_mask |= 1 << val;
438 	pwm.base = of_iomap(np, 0);
439 	if (!pwm.base) {
444 	pwm.timerclk = of_clk_get_by_name(np, "timers");
445 	if (IS_ERR(pwm.timerclk)) {
447 		ret = PTR_ERR(pwm.timerclk);
458 	clk_put(pwm.timerclk);
459 	pwm.timerclk = NULL;
461 	iounmap(pwm.base);
462 	pwm.base = NULL;
478 TIMER_OF_DECLARE(s3c2410_pwm, "samsung,s3c2410-pwm", s3c2410_pwm_clocksource_init);
491 TIMER_OF_DECLARE(s3c6400_pwm, "samsung,s3c6400-pwm", s3c64xx_pwm_clocksource_init);
504 TIMER_OF_DECLARE(s5p6440_pwm, "samsung,s5p6440-pwm", s5p64x0_pwm_clocksource_init);
517 TIMER_OF_DECLARE(s5pc100_pwm, "samsung,s5pc100-pwm", s5p_pwm_clocksource_init);