drivers/clocksource/dw_apb_timer.c

49 static inline u32 apbt_readl(struct dw_apb_timer *timer, unsigned long offs)
51 	return readl(timer->base + offs);
54 static inline void apbt_writel(struct dw_apb_timer *timer, u32 val,
57 	writel(val, timer->base + offs);
60 static inline u32 apbt_readl_relaxed(struct dw_apb_timer *timer, unsigned long offs)
62 	return readl_relaxed(timer->base + offs);
65 static inline void apbt_writel_relaxed(struct dw_apb_timer *timer, u32 val,
68 	writel_relaxed(val, timer->base + offs);
71 static void apbt_disable_int(struct dw_apb_timer *timer)
73 	u32 ctrl = apbt_readl(timer, APBTMR_N_CONTROL);
76 	apbt_writel(timer, ctrl, APBTMR_N_CONTROL);
86 	disable_irq(dw_ced->timer.irq);
87 	apbt_disable_int(&dw_ced->timer);
90 static void apbt_eoi(struct dw_apb_timer *timer)
92 	apbt_readl_relaxed(timer, APBTMR_N_EOI);
101 		pr_info("Spurious APBT timer interrupt %d\n", irq);
106 		dw_ced->eoi(&dw_ced->timer);
112 static void apbt_enable_int(struct dw_apb_timer *timer)
114 	u32 ctrl = apbt_readl(timer, APBTMR_N_CONTROL);
116 	apbt_readl(timer, APBTMR_N_EOI);
118 	apbt_writel(timer, ctrl, APBTMR_N_CONTROL);
129 	ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
131 	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
143 	ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
145 	 * set free running mode, this mode will let timer reload max
152 	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
154 	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
160 	apbt_writel(&dw_ced->timer, ~0, APBTMR_N_LOAD_COUNT);
163 	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
170 	unsigned long period = DIV_ROUND_UP(dw_ced->timer.freq, HZ);
176 	ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL);
178 	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
180 	 * DW APB p. 46, have to disable timer before load counter,
184 	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
187 	apbt_writel(&dw_ced->timer, period, APBTMR_N_LOAD_COUNT);
189 	apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
200 	apbt_enable_int(&dw_ced->timer);
210 	/* Disable timer */
211 	ctrl = apbt_readl_relaxed(&dw_ced->timer, APBTMR_N_CONTROL);
213 	apbt_writel_relaxed(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
215 	apbt_writel_relaxed(&dw_ced->timer, delta, APBTMR_N_LOAD_COUNT);
217 	apbt_writel_relaxed(&dw_ced->timer, ctrl, APBTMR_N_CONTROL);
223  * dw_apb_clockevent_init() - use an APB timer as a clock_event_device
227  * @name:	The name used for the timer and the IRQ for it.
228  * @rating:	The rating to give the timer.
229  * @base:	I/O base for the timer registers.
230  * @irq:	The interrupt number to use for the timer.
231  * @freq:	The frequency that the timer counts at.
236  * it has been called for a timer then the IRQ will be requested, if not it
251 	dw_ced->timer.base = base;
252 	dw_ced->timer.irq = irq;
253 	dw_ced->timer.freq = freq;
270 	dw_ced->ced.irq = dw_ced->timer.irq;
279 		pr_err("failed to request timer irq\n");
294 	enable_irq(dw_ced->timer.irq);
304 	free_irq(dw_ced->timer.irq, &dw_ced->ced);
314 	apbt_writel(&dw_ced->timer, 0, APBTMR_N_CONTROL);
316 	apbt_enable_int(&dw_ced->timer);
333 	u32 ctrl = apbt_readl(&dw_cs->timer, APBTMR_N_CONTROL);
336 	apbt_writel(&dw_cs->timer, ctrl, APBTMR_N_CONTROL);
337 	apbt_writel(&dw_cs->timer, ~0, APBTMR_N_LOAD_COUNT);
341 	apbt_writel(&dw_cs->timer, ctrl, APBTMR_N_CONTROL);
352 	current_count = apbt_readl_relaxed(&dw_cs->timer,
367  * dw_apb_clocksource_init() - use an APB timer as a clocksource.
371  * @base:	The I/O base for the timer registers.
372  * @freq:	The frequency that the timer counts at.
374  * This creates a clocksource using an APB timer but does not yet register it
387 	dw_cs->timer.base = base;
388 	dw_cs->timer.freq = freq;
406 	clocksource_register_hz(&dw_cs->cs, dw_cs->timer.freq);
416 	return (u64)~apbt_readl(&dw_cs->timer, APBTMR_N_CURRENT_VALUE);