clk/xilinx/clk-xlnx-clock-wizard.c

196 	u32 div, p5en, edge, prediv2, all;
200 	p5en = !!(readl(div_addr) & WZRD_P5EN);
209 		div = 2 * all + prediv2 * p5en;
235 	u32 value, regh, edged, p5en, p5fedge, regval, regval1;
252 	p5en = value % 2;
253 	regval1 = regval1 | p5en << WZRD_P5EN_SHIFT | p5fedge << WZRD_P5FEDGE_SHIFT;
433 	u32 regh, edged, p5en, p5fedge, value2, m, regval, regval1, value;
483 	p5en = value % WZRD_DUTY_CYCLE;
485 	regval1 = regval1 | FIELD_PREP(WZRD_P5EN, p5en) | FIELD_PREP(WZRD_P5FEDGE, p5fedge);
586 	u32 edged, div2, p5en, edge, prediv2, all, regl, regh, mult;
614 	p5en = FIELD_GET(WZRD_P5EN, reg);
627 		div2 = PREDIV2_MULT * all + p5en;