Lines Matching refs:NULL
29 { OMAP5_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
34 { OMAP5_MMU_DSP_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_iva_h11x2_ck" },
40 NULL,
56 NULL,
63 NULL,
67 { 24, TI_CLK_MUX, omap5_dmic_gfclk_parents, NULL },
68 { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
76 NULL,
80 { 24, TI_CLK_MUX, omap5_mcbsp1_gfclk_parents, NULL },
81 { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
89 NULL,
93 { 24, TI_CLK_MUX, omap5_mcbsp2_gfclk_parents, NULL },
94 { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
102 NULL,
106 { 24, TI_CLK_MUX, omap5_mcbsp3_gfclk_parents, NULL },
107 { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
114 NULL,
118 { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
123 { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
128 { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
133 { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
138 { OMAP5_L4_ABE_CLKCTRL, NULL, 0, "abe_iclk" },
140 { OMAP5_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" },
153 { OMAP5_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" },
158 { OMAP5_L3_MAIN_2_CLKCTRL, NULL, 0, "l3_iclk_div" },
159 { OMAP5_L3_MAIN_2_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
160 { OMAP5_L3_MAIN_2_OCMC_RAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
165 { OMAP5_MMU_IPU_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_core_h22x2_ck" },
170 { OMAP5_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" },
175 { OMAP5_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" },
176 { OMAP5_EMIF1_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h11x2_ck" },
177 { OMAP5_EMIF2_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h11x2_ck" },
182 { OMAP5_L4_CFG_CLKCTRL, NULL, 0, "l4_root_clk_div" },
183 { OMAP5_SPINLOCK_CLKCTRL, NULL, 0, "l4_root_clk_div" },
184 { OMAP5_MAILBOX_CLKCTRL, NULL, 0, "l4_root_clk_div" },
189 { OMAP5_L3_MAIN_3_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
190 { OMAP5_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
197 NULL,
201 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
206 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
211 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
216 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
221 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
226 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
232 NULL,
236 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
241 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
246 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
251 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
256 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
261 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
266 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
282 { OMAP5_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
283 { OMAP5_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
284 { OMAP5_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
285 { OMAP5_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
286 { OMAP5_L4_PER_CLKCTRL, NULL, 0, "l4_root_clk_div" },
287 { OMAP5_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
288 { OMAP5_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
289 { OMAP5_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
290 { OMAP5_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
293 { OMAP5_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
294 { OMAP5_MMC4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
295 { OMAP5_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
296 { OMAP5_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
297 { OMAP5_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
298 { OMAP5_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
299 { OMAP5_MMC5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
300 { OMAP5_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
301 { OMAP5_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
302 { OMAP5_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
308 { OMAP5_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
309 { OMAP5_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
310 { OMAP5_DES3DES_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
311 { OMAP5_FPKA_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div" },
312 { OMAP5_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l4_root_clk_div" },
313 { OMAP5_SHA2MD5_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
314 { OMAP5_DMA_CRYPTO_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l3_iclk_div" },
319 { OMAP5_IVA_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" },
320 { OMAP5_SL2IF_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h12x2_ck" },
326 NULL,
331 NULL,
336 NULL,
340 { 8, TI_CLK_GATE, omap5_dss_dss_clk_parents, NULL },
341 { 9, TI_CLK_GATE, omap5_dss_48mhz_clk_parents, NULL },
342 { 10, TI_CLK_GATE, omap5_dss_sys_clk_parents, NULL },
343 { 11, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
355 NULL,
361 NULL,
366 NULL,
374 { 24, TI_CLK_MUX, omap5_gpu_core_mux_parents, NULL },
375 { 25, TI_CLK_MUX, omap5_gpu_hyd_mux_parents, NULL },
388 NULL,
393 NULL,
401 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
402 { 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL },
409 NULL,
417 { 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL },
424 NULL,
429 NULL,
434 NULL,
439 NULL,
445 NULL,
451 NULL,
455 { 6, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
456 { 7, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
457 { 8, TI_CLK_GATE, omap5_usb_host_hs_utmi_p1_clk_parents, NULL },
458 { 9, TI_CLK_GATE, omap5_usb_host_hs_utmi_p2_clk_parents, NULL },
459 { 10, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
460 { 11, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
461 { 12, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
462 { 13, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
463 { 14, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
464 { 24, TI_CLK_MUX, omap5_utmi_p1_gfclk_parents, NULL },
465 { 25, TI_CLK_MUX, omap5_utmi_p2_gfclk_parents, NULL },
470 { 8, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
471 { 9, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
472 { 10, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
478 NULL,
482 { 8, TI_CLK_GATE, omap5_sata_ref_clk_parents, NULL },
488 NULL,
492 { 8, TI_CLK_GATE, omap5_usb_otg_ss_refclk960m_parents, NULL },
502 { OMAP5_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
503 { OMAP5_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
509 { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
514 { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
519 { OMAP5_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
520 { OMAP5_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
523 { OMAP5_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
524 { OMAP5_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
550 DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
551 DT_CLK(NULL, "sys_clkin_ck", "sys_clkin"),
552 DT_CLK(NULL, "dmic_gfclk", "abe-clkctrl:0018:24"),
553 DT_CLK(NULL, "dmic_sync_mux_ck", "abe-clkctrl:0018:26"),
554 DT_CLK(NULL, "dss_32khz_clk", "dss-clkctrl:0000:11"),
555 DT_CLK(NULL, "dss_48mhz_clk", "dss-clkctrl:0000:9"),
556 DT_CLK(NULL, "dss_dss_clk", "dss-clkctrl:0000:8"),
557 DT_CLK(NULL, "dss_sys_clk", "dss-clkctrl:0000:10"),
558 DT_CLK(NULL, "gpio1_dbclk", "wkupaon-clkctrl:0018:8"),
559 DT_CLK(NULL, "gpio2_dbclk", "l4per-clkctrl:0040:8"),
560 DT_CLK(NULL, "gpio3_dbclk", "l4per-clkctrl:0048:8"),
561 DT_CLK(NULL, "gpio4_dbclk", "l4per-clkctrl:0050:8"),
562 DT_CLK(NULL, "gpio5_dbclk", "l4per-clkctrl:0058:8"),
563 DT_CLK(NULL, "gpio6_dbclk", "l4per-clkctrl:0060:8"),
564 DT_CLK(NULL, "gpio7_dbclk", "l4per-clkctrl:00f0:8"),
565 DT_CLK(NULL, "gpio8_dbclk", "l4per-clkctrl:00f8:8"),
566 DT_CLK(NULL, "mcbsp1_gfclk", "abe-clkctrl:0028:24"),
567 DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe-clkctrl:0028:26"),
569 DT_CLK(NULL, "mcbsp2_gfclk", "abe-clkctrl:0030:24"),
570 DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe-clkctrl:0030:26"),
572 DT_CLK(NULL, "mcbsp3_gfclk", "abe-clkctrl:0038:24"),
573 DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe-clkctrl:0038:26"),
575 DT_CLK(NULL, "mmc1_32khz_clk", "l3init-clkctrl:0008:8"),
576 DT_CLK(NULL, "mmc1_fclk", "l3init-clkctrl:0008:25"),
577 DT_CLK(NULL, "mmc1_fclk_mux", "l3init-clkctrl:0008:24"),
578 DT_CLK(NULL, "mmc2_fclk", "l3init-clkctrl:0010:25"),
579 DT_CLK(NULL, "mmc2_fclk_mux", "l3init-clkctrl:0010:24"),
580 DT_CLK(NULL, "pad_fck", "pad_clks_ck"),
581 DT_CLK(NULL, "sata_ref_clk", "l3init-clkctrl:0068:8"),
582 DT_CLK(NULL, "timer10_gfclk_mux", "l4per-clkctrl:0008:24"),
583 DT_CLK(NULL, "timer11_gfclk_mux", "l4per-clkctrl:0010:24"),
584 DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon-clkctrl:0020:24"),
585 DT_CLK(NULL, "timer2_gfclk_mux", "l4per-clkctrl:0018:24"),
586 DT_CLK(NULL, "timer3_gfclk_mux", "l4per-clkctrl:0020:24"),
587 DT_CLK(NULL, "timer4_gfclk_mux", "l4per-clkctrl:0028:24"),
588 DT_CLK(NULL, "timer5_gfclk_mux", "abe-clkctrl:0048:24"),
589 DT_CLK(NULL, "timer6_gfclk_mux", "abe-clkctrl:0050:24"),
590 DT_CLK(NULL, "timer7_gfclk_mux", "abe-clkctrl:0058:24"),
591 DT_CLK(NULL, "timer8_gfclk_mux", "abe-clkctrl:0060:24"),
592 DT_CLK(NULL, "timer9_gfclk_mux", "l4per-clkctrl:0030:24"),
593 DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3init-clkctrl:0038:13"),
594 DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3init-clkctrl:0038:14"),
595 DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "l3init-clkctrl:0038:7"),
596 DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3init-clkctrl:0038:11"),
597 DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3init-clkctrl:0038:12"),
598 DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "l3init-clkctrl:0038:6"),
599 DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3init-clkctrl:0038:8"),
600 DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3init-clkctrl:0038:9"),
601 DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3init-clkctrl:0038:10"),
602 DT_CLK(NULL, "usb_otg_ss_refclk960m", "l3init-clkctrl:00d0:8"),
603 DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3init-clkctrl:0048:8"),
604 DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3init-clkctrl:0048:9"),
605 DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3init-clkctrl:0048:10"),
606 DT_CLK(NULL, "utmi_p1_gfclk", "l3init-clkctrl:0038:24"),
607 DT_CLK(NULL, "utmi_p2_gfclk", "l3init-clkctrl:0038:25"),
608 { .node_name = NULL },
622 abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_clk_mux");
623 sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
631 abe_dpll_byp = clk_get_sys(NULL, "abe_dpll_bypass_clk_mux");
635 abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
641 abe_dpll = clk_get_sys(NULL, "dpll_abe_m2x2_ck");
647 usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
652 usb_dpll = clk_get_sys(NULL, "dpll_usb_m2_ck");