clk/ti/clk-44xx.c

35 	{ OMAP4_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
40 	{ OMAP4_DSP_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_iva_m4x2_ck" },
46 	NULL,
62 	NULL,
69 	NULL,
73 	{ 24, TI_CLK_MUX, omap4_func_dmic_abe_gfclk_parents, NULL },
74 	{ 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
82 	NULL,
86 	{ 24, TI_CLK_MUX, omap4_func_mcasp_abe_gfclk_parents, NULL },
87 	{ 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
95 	NULL,
99 	{ 24, TI_CLK_MUX, omap4_func_mcbsp1_gfclk_parents, NULL },
100 	{ 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
108 	NULL,
112 	{ 24, TI_CLK_MUX, omap4_func_mcbsp2_gfclk_parents, NULL },
113 	{ 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
121 	NULL,
125 	{ 24, TI_CLK_MUX, omap4_func_mcbsp3_gfclk_parents, NULL },
126 	{ 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
132 	NULL,
137 	NULL,
142 	NULL,
147 	NULL,
151 	{ 8, TI_CLK_GATE, omap4_slimbus1_fclk_0_parents, NULL },
152 	{ 9, TI_CLK_GATE, omap4_slimbus1_fclk_1_parents, NULL },
153 	{ 10, TI_CLK_GATE, omap4_slimbus1_fclk_2_parents, NULL },
154 	{ 11, TI_CLK_GATE, omap4_slimbus1_slimbus_clk_parents, NULL },
161 	NULL,
165 	{ 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
170 	{ 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
175 	{ 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
180 	{ 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
185 	{ OMAP4_L4_ABE_CLKCTRL, NULL, 0, "ocp_abe_iclk" },
187 	{ OMAP4_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" },
198 	{ OMAP4_WD_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
203 	{ OMAP4_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "l4_wkup_clk_mux_ck" },
204 	{ OMAP4_SMARTREFLEX_IVA_CLKCTRL, NULL, CLKF_SW_SUP, "l4_wkup_clk_mux_ck" },
205 	{ OMAP4_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "l4_wkup_clk_mux_ck" },
210 	{ OMAP4_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_div_ck" },
215 	{ OMAP4_L3_MAIN_2_CLKCTRL, NULL, 0, "l3_div_ck" },
216 	{ OMAP4_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_div_ck" },
217 	{ OMAP4_OCMC_RAM_CLKCTRL, NULL, 0, "l3_div_ck" },
222 	{ OMAP4_IPU_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "ducati_clk_mux_ck" },
227 	{ OMAP4_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_div_ck" },
232 	{ OMAP4_DMM_CLKCTRL, NULL, 0, "l3_div_ck" },
233 	{ OMAP4_EMIF1_CLKCTRL, NULL, CLKF_HW_SUP, "ddrphy_ck" },
234 	{ OMAP4_EMIF2_CLKCTRL, NULL, CLKF_HW_SUP, "ddrphy_ck" },
239 	{ OMAP4_C2C_CLKCTRL, NULL, 0, "div_core_ck" },
244 	{ OMAP4_L4_CFG_CLKCTRL, NULL, 0, "l4_div_ck" },
245 	{ OMAP4_SPINLOCK_CLKCTRL, NULL, 0, "l4_div_ck" },
246 	{ OMAP4_MAILBOX_CLKCTRL, NULL, 0, "l4_div_ck" },
251 	{ OMAP4_L3_MAIN_3_CLKCTRL, NULL, CLKF_HW_SUP, "l3_div_ck" },
252 	{ OMAP4_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_div_ck" },
253 	{ OMAP4_OCP_WP_NOC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_div_ck" },
258 	{ OMAP4_IVA_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_NO_IDLEST, "dpll_iva_m5x2_ck" },
259 	{ OMAP4_SL2IF_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_m5x2_ck" },
265 	NULL,
269 	{ 8, TI_CLK_GATE, omap4_iss_ctrlclk_parents, NULL },
275 	NULL,
296 	NULL,
301 	NULL,
306 	NULL,
311 	NULL,
315 	{ 8, TI_CLK_GATE, omap4_dss_dss_clk_parents, NULL },
316 	{ 9, TI_CLK_GATE, omap4_dss_48mhz_clk_parents, NULL },
317 	{ 10, TI_CLK_GATE, omap4_dss_sys_clk_parents, NULL },
318 	{ 11, TI_CLK_GATE, omap4_dss_tv_clk_parents, NULL },
330 	NULL,
334 	{ 24, TI_CLK_MUX, omap4_sgx_clk_mux_parents, NULL },
346 	NULL,
350 	{ 24, TI_CLK_MUX, omap4_hsmmc1_fclk_parents, NULL },
355 	{ 24, TI_CLK_MUX, omap4_hsmmc1_fclk_parents, NULL },
361 	NULL,
376 	NULL,
381 	NULL,
386 	NULL,
391 	NULL,
397 	NULL,
403 	NULL,
407 	{ 8, TI_CLK_GATE, omap4_usb_host_hs_utmi_p1_clk_parents, NULL },
408 	{ 9, TI_CLK_GATE, omap4_usb_host_hs_utmi_p2_clk_parents, NULL },
409 	{ 10, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
410 	{ 11, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
411 	{ 12, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
412 	{ 13, TI_CLK_GATE, omap4_usb_host_hs_hsic480m_p1_clk_parents, NULL },
413 	{ 14, TI_CLK_GATE, omap4_usb_host_hs_hsic480m_p1_clk_parents, NULL },
414 	{ 15, TI_CLK_GATE, omap4_dss_48mhz_clk_parents, NULL },
415 	{ 24, TI_CLK_MUX, omap4_utmi_p1_gfclk_parents, NULL },
416 	{ 25, TI_CLK_MUX, omap4_utmi_p2_gfclk_parents, NULL },
422 	NULL,
428 	NULL,
432 	{ 8, TI_CLK_GATE, omap4_usb_otg_hs_xclk_parents, NULL },
433 	{ 24, TI_CLK_MUX, omap4_otg_60m_gfclk_parents, NULL },
438 	{ 8, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
439 	{ 9, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
440 	{ 10, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
446 	NULL,
450 	{ 8, TI_CLK_GATE, omap4_ocp2scp_usb_phy_phy_48m_parents, NULL },
461 	{ OMAP4_USB_HOST_FS_CLKCTRL, NULL, CLKF_SW_SUP, "func_48mc_fclk" },
469 	NULL,
473 	{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
478 	{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
483 	{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
488 	{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
493 	{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
498 	{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
504 	NULL,
508 	{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
513 	{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
518 	{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
523 	{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
528 	{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
535 	NULL,
541 	NULL,
545 	{ 24, TI_CLK_MUX, omap4_per_mcbsp4_gfclk_parents, NULL },
546 	{ 26, TI_CLK_MUX, omap4_mcbsp4_sync_mux_ck_parents, NULL },
552 	NULL,
557 	NULL,
562 	NULL,
566 	{ 8, TI_CLK_GATE, omap4_slimbus2_fclk_0_parents, NULL },
567 	{ 9, TI_CLK_GATE, omap4_slimbus2_fclk_1_parents, NULL },
568 	{ 10, TI_CLK_GATE, omap4_slimbus2_slimbus_clk_parents, NULL },
579 	{ OMAP4_ELM_CLKCTRL, NULL, 0, "l4_div_ck" },
585 	{ OMAP4_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" },
586 	{ OMAP4_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
587 	{ OMAP4_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
588 	{ OMAP4_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
589 	{ OMAP4_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
590 	{ OMAP4_L4_PER_CLKCTRL, NULL, 0, "l4_div_ck" },
592 	{ OMAP4_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
593 	{ OMAP4_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
594 	{ OMAP4_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
595 	{ OMAP4_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
596 	{ OMAP4_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
597 	{ OMAP4_MMC4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
599 	{ OMAP4_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
600 	{ OMAP4_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
601 	{ OMAP4_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
602 	{ OMAP4_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
603 	{ OMAP4_MMC5_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
609 	{ OMAP4_AES1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_div_ck" },
610 	{ OMAP4_AES2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_div_ck" },
611 	{ OMAP4_DES3DES_CLKCTRL, NULL, CLKF_SW_SUP, "l4_div_ck" },
612 	{ OMAP4_PKA_CLKCTRL, NULL, CLKF_SW_SUP, "l4_div_ck" },
613 	{ OMAP4_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l4_div_ck" },
614 	{ OMAP4_SHA2MD5_CLKCTRL, NULL, CLKF_SW_SUP, "l3_div_ck" },
615 	{ OMAP4_CRYPTODMA_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l3_div_ck" },
620 	{ 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
625 	{ 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
630 	{ OMAP4_L4_WKUP_CLKCTRL, NULL, 0, "l4_wkup_clk_mux_ck" },
631 	{ OMAP4_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
634 	{ OMAP4_COUNTER_32K_CLKCTRL, NULL, 0, "sys_32k_ck" },
635 	{ OMAP4_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
643 	NULL,
648 	NULL,
666 	NULL,
675 	{ 20, TI_CLK_MUX, omap4_pmd_stm_clock_mux_ck_parents, NULL },
676 	{ 22, TI_CLK_MUX, omap4_pmd_stm_clock_mux_ck_parents, NULL },
713 	DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
719 	DT_CLK(NULL, "aess_fclk", "abe-clkctrl:0008:24"),
720 	DT_CLK(NULL, "cm2_dm10_mux", "l4-per-clkctrl:0008:24"),
721 	DT_CLK(NULL, "cm2_dm11_mux", "l4-per-clkctrl:0010:24"),
722 	DT_CLK(NULL, "cm2_dm2_mux", "l4-per-clkctrl:0018:24"),
723 	DT_CLK(NULL, "cm2_dm3_mux", "l4-per-clkctrl:0020:24"),
724 	DT_CLK(NULL, "cm2_dm4_mux", "l4-per-clkctrl:0028:24"),
725 	DT_CLK(NULL, "cm2_dm9_mux", "l4-per-clkctrl:0030:24"),
726 	DT_CLK(NULL, "dmic_sync_mux_ck", "abe-clkctrl:0018:26"),
727 	DT_CLK(NULL, "dmt1_clk_mux", "l4-wkup-clkctrl:0020:24"),
728 	DT_CLK(NULL, "dss_48mhz_clk", "l3-dss-clkctrl:0000:9"),
729 	DT_CLK(NULL, "dss_dss_clk", "l3-dss-clkctrl:0000:8"),
730 	DT_CLK(NULL, "dss_sys_clk", "l3-dss-clkctrl:0000:10"),
731 	DT_CLK(NULL, "dss_tv_clk", "l3-dss-clkctrl:0000:11"),
732 	DT_CLK(NULL, "fdif_fck", "iss-clkctrl:0008:24"),
733 	DT_CLK(NULL, "func_dmic_abe_gfclk", "abe-clkctrl:0018:24"),
734 	DT_CLK(NULL, "func_mcasp_abe_gfclk", "abe-clkctrl:0020:24"),
735 	DT_CLK(NULL, "func_mcbsp1_gfclk", "abe-clkctrl:0028:24"),
736 	DT_CLK(NULL, "func_mcbsp2_gfclk", "abe-clkctrl:0030:24"),
737 	DT_CLK(NULL, "func_mcbsp3_gfclk", "abe-clkctrl:0038:24"),
738 	DT_CLK(NULL, "gpio1_dbclk", "l4-wkup-clkctrl:0018:8"),
739 	DT_CLK(NULL, "gpio2_dbclk", "l4-per-clkctrl:0040:8"),
740 	DT_CLK(NULL, "gpio3_dbclk", "l4-per-clkctrl:0048:8"),
741 	DT_CLK(NULL, "gpio4_dbclk", "l4-per-clkctrl:0050:8"),
742 	DT_CLK(NULL, "gpio5_dbclk", "l4-per-clkctrl:0058:8"),
743 	DT_CLK(NULL, "gpio6_dbclk", "l4-per-clkctrl:0060:8"),
744 	DT_CLK(NULL, "hsi_fck", "l3-init-clkctrl:0018:24"),
745 	DT_CLK(NULL, "hsmmc1_fclk", "l3-init-clkctrl:0008:24"),
746 	DT_CLK(NULL, "hsmmc2_fclk", "l3-init-clkctrl:0010:24"),
747 	DT_CLK(NULL, "iss_ctrlclk", "iss-clkctrl:0000:8"),
748 	DT_CLK(NULL, "mcasp_sync_mux_ck", "abe-clkctrl:0020:26"),
749 	DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe-clkctrl:0028:26"),
750 	DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe-clkctrl:0030:26"),
751 	DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe-clkctrl:0038:26"),
755 	DT_CLK(NULL, "mcbsp4_sync_mux_ck", "l4-per-clkctrl:00c0:26"),
757 	DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "l3-init-clkctrl:00c0:8"),
758 	DT_CLK(NULL, "otg_60m_gfclk", "l3-init-clkctrl:0040:24"),
759 	DT_CLK(NULL, "pad_fck", "pad_clks_ck"),
760 	DT_CLK(NULL, "per_mcbsp4_gfclk", "l4-per-clkctrl:00c0:24"),
761 	DT_CLK(NULL, "pmd_stm_clock_mux_ck", "emu-sys-clkctrl:0000:20"),
762 	DT_CLK(NULL, "pmd_trace_clk_mux_ck", "emu-sys-clkctrl:0000:22"),
763 	DT_CLK(NULL, "sgx_clk_mux", "l3-gfx-clkctrl:0000:24"),
764 	DT_CLK(NULL, "slimbus1_fclk_0", "abe-clkctrl:0040:8"),
765 	DT_CLK(NULL, "slimbus1_fclk_1", "abe-clkctrl:0040:9"),
766 	DT_CLK(NULL, "slimbus1_fclk_2", "abe-clkctrl:0040:10"),
767 	DT_CLK(NULL, "slimbus1_slimbus_clk", "abe-clkctrl:0040:11"),
768 	DT_CLK(NULL, "slimbus2_fclk_0", "l4-per-clkctrl:0118:8"),
769 	DT_CLK(NULL, "slimbus2_fclk_1", "l4-per-clkctrl:0118:9"),
770 	DT_CLK(NULL, "slimbus2_slimbus_clk", "l4-per-clkctrl:0118:10"),
771 	DT_CLK(NULL, "stm_clk_div_ck", "emu-sys-clkctrl:0000:27"),
772 	DT_CLK(NULL, "timer5_sync_mux", "abe-clkctrl:0048:24"),
773 	DT_CLK(NULL, "timer6_sync_mux", "abe-clkctrl:0050:24"),
774 	DT_CLK(NULL, "timer7_sync_mux", "abe-clkctrl:0058:24"),
775 	DT_CLK(NULL, "timer8_sync_mux", "abe-clkctrl:0060:24"),
776 	DT_CLK(NULL, "trace_clk_div_div_ck", "emu-sys-clkctrl:0000:24"),
777 	DT_CLK(NULL, "usb_host_hs_func48mclk", "l3-init-clkctrl:0038:15"),
778 	DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3-init-clkctrl:0038:13"),
779 	DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3-init-clkctrl:0038:14"),
780 	DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3-init-clkctrl:0038:11"),
781 	DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3-init-clkctrl:0038:12"),
782 	DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3-init-clkctrl:0038:8"),
783 	DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3-init-clkctrl:0038:9"),
784 	DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3_init-clkctrl:0038:10"),
785 	DT_CLK(NULL, "usb_otg_hs_xclk", "l3-init-clkctrl:0040:8"),
786 	DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3-init-clkctrl:0048:8"),
787 	DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3-init-clkctrl:0048:9"),
788 	DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3-init-clkctrl:0048:10"),
789 	DT_CLK(NULL, "utmi_p1_gfclk", "l3-init-clkctrl:0038:24"),
790 	DT_CLK(NULL, "utmi_p2_gfclk", "l3-init-clkctrl:0038:25"),
791 	{ .node_name = NULL },
809 	usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
820 	abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_refclk_mux_ck");
821 	sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
823 	abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");