Lines Matching refs:present
688 [tegra_clk_clk_32k] = { .dt_id = TEGRA30_CLK_CLK_32K, .present = true },
689 [tegra_clk_clk_m] = { .dt_id = TEGRA30_CLK_CLK_M, .present = true },
690 [tegra_clk_osc] = { .dt_id = TEGRA30_CLK_OSC, .present = true },
691 [tegra_clk_osc_div2] = { .dt_id = TEGRA30_CLK_OSC_DIV2, .present = true },
692 [tegra_clk_osc_div4] = { .dt_id = TEGRA30_CLK_OSC_DIV4, .present = true },
693 [tegra_clk_pll_ref] = { .dt_id = TEGRA30_CLK_PLL_REF, .present = true },
694 [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC, .present = true },
695 [tegra_clk_i2s0_sync] = { .dt_id = TEGRA30_CLK_I2S0_SYNC, .present = true },
696 [tegra_clk_i2s1_sync] = { .dt_id = TEGRA30_CLK_I2S1_SYNC, .present = true },
697 [tegra_clk_i2s2_sync] = { .dt_id = TEGRA30_CLK_I2S2_SYNC, .present = true },
698 [tegra_clk_i2s3_sync] = { .dt_id = TEGRA30_CLK_I2S3_SYNC, .present = true },
699 [tegra_clk_i2s4_sync] = { .dt_id = TEGRA30_CLK_I2S4_SYNC, .present = true },
700 [tegra_clk_vimclk_sync] = { .dt_id = TEGRA30_CLK_VIMCLK_SYNC, .present = true },
701 [tegra_clk_audio0] = { .dt_id = TEGRA30_CLK_AUDIO0, .present = true },
702 [tegra_clk_audio1] = { .dt_id = TEGRA30_CLK_AUDIO1, .present = true },
703 [tegra_clk_audio2] = { .dt_id = TEGRA30_CLK_AUDIO2, .present = true },
704 [tegra_clk_audio3] = { .dt_id = TEGRA30_CLK_AUDIO3, .present = true },
705 [tegra_clk_audio4] = { .dt_id = TEGRA30_CLK_AUDIO4, .present = true },
706 [tegra_clk_spdif] = { .dt_id = TEGRA30_CLK_SPDIF, .present = true },
707 [tegra_clk_audio0_mux] = { .dt_id = TEGRA30_CLK_AUDIO0_MUX, .present = true },
708 [tegra_clk_audio1_mux] = { .dt_id = TEGRA30_CLK_AUDIO1_MUX, .present = true },
709 [tegra_clk_audio2_mux] = { .dt_id = TEGRA30_CLK_AUDIO2_MUX, .present = true },
710 [tegra_clk_audio3_mux] = { .dt_id = TEGRA30_CLK_AUDIO3_MUX, .present = true },
711 [tegra_clk_audio4_mux] = { .dt_id = TEGRA30_CLK_AUDIO4_MUX, .present = true },
712 [tegra_clk_spdif_mux] = { .dt_id = TEGRA30_CLK_SPDIF_MUX, .present = true },
713 [tegra_clk_audio0_2x] = { .dt_id = TEGRA30_CLK_AUDIO0_2X, .present = true },
714 [tegra_clk_audio1_2x] = { .dt_id = TEGRA30_CLK_AUDIO1_2X, .present = true },
715 [tegra_clk_audio2_2x] = { .dt_id = TEGRA30_CLK_AUDIO2_2X, .present = true },
716 [tegra_clk_audio3_2x] = { .dt_id = TEGRA30_CLK_AUDIO3_2X, .present = true },
717 [tegra_clk_audio4_2x] = { .dt_id = TEGRA30_CLK_AUDIO4_2X, .present = true },
718 [tegra_clk_spdif_2x] = { .dt_id = TEGRA30_CLK_SPDIF_2X, .present = true },
719 [tegra_clk_hclk] = { .dt_id = TEGRA30_CLK_HCLK, .present = true },
720 [tegra_clk_pclk] = { .dt_id = TEGRA30_CLK_PCLK, .present = true },
721 [tegra_clk_i2s0] = { .dt_id = TEGRA30_CLK_I2S0, .present = true },
722 [tegra_clk_i2s1] = { .dt_id = TEGRA30_CLK_I2S1, .present = true },
723 [tegra_clk_i2s2] = { .dt_id = TEGRA30_CLK_I2S2, .present = true },
724 [tegra_clk_i2s3] = { .dt_id = TEGRA30_CLK_I2S3, .present = true },
725 [tegra_clk_i2s4] = { .dt_id = TEGRA30_CLK_I2S4, .present = true },
726 [tegra_clk_spdif_in] = { .dt_id = TEGRA30_CLK_SPDIF_IN, .present = true },
727 [tegra_clk_hda] = { .dt_id = TEGRA30_CLK_HDA, .present = true },
728 [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA30_CLK_HDA2CODEC_2X, .present = true },
729 [tegra_clk_sbc1] = { .dt_id = TEGRA30_CLK_SBC1, .present = true },
730 [tegra_clk_sbc2] = { .dt_id = TEGRA30_CLK_SBC2, .present = true },
731 [tegra_clk_sbc3] = { .dt_id = TEGRA30_CLK_SBC3, .present = true },
732 [tegra_clk_sbc4] = { .dt_id = TEGRA30_CLK_SBC4, .present = true },
733 [tegra_clk_sbc5] = { .dt_id = TEGRA30_CLK_SBC5, .present = true },
734 [tegra_clk_sbc6] = { .dt_id = TEGRA30_CLK_SBC6, .present = true },
735 [tegra_clk_ndflash] = { .dt_id = TEGRA30_CLK_NDFLASH, .present = true },
736 [tegra_clk_ndspeed] = { .dt_id = TEGRA30_CLK_NDSPEED, .present = true },
737 [tegra_clk_vfir] = { .dt_id = TEGRA30_CLK_VFIR, .present = true },
738 [tegra_clk_la] = { .dt_id = TEGRA30_CLK_LA, .present = true },
739 [tegra_clk_csite] = { .dt_id = TEGRA30_CLK_CSITE, .present = true },
740 [tegra_clk_owr] = { .dt_id = TEGRA30_CLK_OWR, .present = true },
741 [tegra_clk_mipi] = { .dt_id = TEGRA30_CLK_MIPI, .present = true },
742 [tegra_clk_tsensor] = { .dt_id = TEGRA30_CLK_TSENSOR, .present = true },
743 [tegra_clk_i2cslow] = { .dt_id = TEGRA30_CLK_I2CSLOW, .present = true },
744 [tegra_clk_vde] = { .dt_id = TEGRA30_CLK_VDE, .present = true },
745 [tegra_clk_vi] = { .dt_id = TEGRA30_CLK_VI, .present = true },
746 [tegra_clk_epp] = { .dt_id = TEGRA30_CLK_EPP, .present = true },
747 [tegra_clk_mpe] = { .dt_id = TEGRA30_CLK_MPE, .present = true },
748 [tegra_clk_host1x] = { .dt_id = TEGRA30_CLK_HOST1X, .present = true },
749 [tegra_clk_gr2d] = { .dt_id = TEGRA30_CLK_GR2D, .present = true },
750 [tegra_clk_gr3d] = { .dt_id = TEGRA30_CLK_GR3D, .present = true },
751 [tegra_clk_mselect] = { .dt_id = TEGRA30_CLK_MSELECT, .present = true },
752 [tegra_clk_nor] = { .dt_id = TEGRA30_CLK_NOR, .present = true },
753 [tegra_clk_sdmmc1] = { .dt_id = TEGRA30_CLK_SDMMC1, .present = true },
754 [tegra_clk_sdmmc2] = { .dt_id = TEGRA30_CLK_SDMMC2, .present = true },
755 [tegra_clk_sdmmc3] = { .dt_id = TEGRA30_CLK_SDMMC3, .present = true },
756 [tegra_clk_sdmmc4] = { .dt_id = TEGRA30_CLK_SDMMC4, .present = true },
757 [tegra_clk_cve] = { .dt_id = TEGRA30_CLK_CVE, .present = true },
758 [tegra_clk_tvo] = { .dt_id = TEGRA30_CLK_TVO, .present = true },
759 [tegra_clk_tvdac] = { .dt_id = TEGRA30_CLK_TVDAC, .present = true },
760 [tegra_clk_actmon] = { .dt_id = TEGRA30_CLK_ACTMON, .present = true },
761 [tegra_clk_vi_sensor] = { .dt_id = TEGRA30_CLK_VI_SENSOR, .present = true },
762 [tegra_clk_i2c1] = { .dt_id = TEGRA30_CLK_I2C1, .present = true },
763 [tegra_clk_i2c2] = { .dt_id = TEGRA30_CLK_I2C2, .present = true },
764 [tegra_clk_i2c3] = { .dt_id = TEGRA30_CLK_I2C3, .present = true },
765 [tegra_clk_i2c4] = { .dt_id = TEGRA30_CLK_I2C4, .present = true },
766 [tegra_clk_i2c5] = { .dt_id = TEGRA30_CLK_I2C5, .present = true },
767 [tegra_clk_uarta] = { .dt_id = TEGRA30_CLK_UARTA, .present = true },
768 [tegra_clk_uartb] = { .dt_id = TEGRA30_CLK_UARTB, .present = true },
769 [tegra_clk_uartc] = { .dt_id = TEGRA30_CLK_UARTC, .present = true },
770 [tegra_clk_uartd] = { .dt_id = TEGRA30_CLK_UARTD, .present = true },
771 [tegra_clk_uarte] = { .dt_id = TEGRA30_CLK_UARTE, .present = true },
772 [tegra_clk_extern1] = { .dt_id = TEGRA30_CLK_EXTERN1, .present = true },
773 [tegra_clk_extern2] = { .dt_id = TEGRA30_CLK_EXTERN2, .present = true },
774 [tegra_clk_extern3] = { .dt_id = TEGRA30_CLK_EXTERN3, .present = true },
775 [tegra_clk_disp1] = { .dt_id = TEGRA30_CLK_DISP1, .present = true },
776 [tegra_clk_disp2] = { .dt_id = TEGRA30_CLK_DISP2, .present = true },
777 [tegra_clk_ahbdma] = { .dt_id = TEGRA30_CLK_AHBDMA, .present = true },
778 [tegra_clk_apbdma] = { .dt_id = TEGRA30_CLK_APBDMA, .present = true },
779 [tegra_clk_rtc] = { .dt_id = TEGRA30_CLK_RTC, .present = true },
780 [tegra_clk_timer] = { .dt_id = TEGRA30_CLK_TIMER, .present = true },
781 [tegra_clk_kbc] = { .dt_id = TEGRA30_CLK_KBC, .present = true },
782 [tegra_clk_csus] = { .dt_id = TEGRA30_CLK_CSUS, .present = true },
783 [tegra_clk_vcp] = { .dt_id = TEGRA30_CLK_VCP, .present = true },
784 [tegra_clk_bsea] = { .dt_id = TEGRA30_CLK_BSEA, .present = true },
785 [tegra_clk_bsev] = { .dt_id = TEGRA30_CLK_BSEV, .present = true },
786 [tegra_clk_usbd] = { .dt_id = TEGRA30_CLK_USBD, .present = true },
787 [tegra_clk_usb2] = { .dt_id = TEGRA30_CLK_USB2, .present = true },
788 [tegra_clk_usb3] = { .dt_id = TEGRA30_CLK_USB3, .present = true },
789 [tegra_clk_csi] = { .dt_id = TEGRA30_CLK_CSI, .present = true },
790 [tegra_clk_isp] = { .dt_id = TEGRA30_CLK_ISP, .present = true },
791 [tegra_clk_kfuse] = { .dt_id = TEGRA30_CLK_KFUSE, .present = true },
792 [tegra_clk_fuse] = { .dt_id = TEGRA30_CLK_FUSE, .present = true },
793 [tegra_clk_fuse_burn] = { .dt_id = TEGRA30_CLK_FUSE_BURN, .present = true },
794 [tegra_clk_apbif] = { .dt_id = TEGRA30_CLK_APBIF, .present = true },
795 [tegra_clk_hda2hdmi] = { .dt_id = TEGRA30_CLK_HDA2HDMI, .present = true },
796 [tegra_clk_sata_cold] = { .dt_id = TEGRA30_CLK_SATA_COLD, .present = true },
797 [tegra_clk_sata_oob] = { .dt_id = TEGRA30_CLK_SATA_OOB, .present = true },
798 [tegra_clk_sata] = { .dt_id = TEGRA30_CLK_SATA, .present = true },
799 [tegra_clk_dtv] = { .dt_id = TEGRA30_CLK_DTV, .present = true },
800 [tegra_clk_pll_p] = { .dt_id = TEGRA30_CLK_PLL_P, .present = true },
801 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA30_CLK_PLL_P_OUT1, .present = true },
802 [tegra_clk_pll_p_out2] = { .dt_id = TEGRA30_CLK_PLL_P_OUT2, .present = true },
803 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA30_CLK_PLL_P_OUT3, .present = true },
804 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA30_CLK_PLL_P_OUT4, .present = true },
805 [tegra_clk_pll_a] = { .dt_id = TEGRA30_CLK_PLL_A, .present = true },
806 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA30_CLK_PLL_A_OUT0, .present = true },
807 [tegra_clk_cec] = { .dt_id = TEGRA30_CLK_CEC, .present = true },
808 [tegra_clk_emc] = { .dt_id = TEGRA30_CLK_EMC, .present = false },