Lines Matching refs:present
22 * banks present in the Tegra124/132 CAR IP block. The banks are
748 [tegra_clk_ispb] = { .dt_id = TEGRA124_CLK_ISPB, .present = true },
749 [tegra_clk_rtc] = { .dt_id = TEGRA124_CLK_RTC, .present = true },
750 [tegra_clk_timer] = { .dt_id = TEGRA124_CLK_TIMER, .present = true },
751 [tegra_clk_uarta] = { .dt_id = TEGRA124_CLK_UARTA, .present = true },
752 [tegra_clk_sdmmc2_8] = { .dt_id = TEGRA124_CLK_SDMMC2, .present = true },
753 [tegra_clk_i2s1] = { .dt_id = TEGRA124_CLK_I2S1, .present = true },
754 [tegra_clk_i2c1] = { .dt_id = TEGRA124_CLK_I2C1, .present = true },
755 [tegra_clk_sdmmc1_8] = { .dt_id = TEGRA124_CLK_SDMMC1, .present = true },
756 [tegra_clk_sdmmc4_8] = { .dt_id = TEGRA124_CLK_SDMMC4, .present = true },
757 [tegra_clk_pwm] = { .dt_id = TEGRA124_CLK_PWM, .present = true },
758 [tegra_clk_i2s2] = { .dt_id = TEGRA124_CLK_I2S2, .present = true },
759 [tegra_clk_usbd] = { .dt_id = TEGRA124_CLK_USBD, .present = true },
760 [tegra_clk_isp_8] = { .dt_id = TEGRA124_CLK_ISP, .present = true },
761 [tegra_clk_disp2] = { .dt_id = TEGRA124_CLK_DISP2, .present = true },
762 [tegra_clk_disp1] = { .dt_id = TEGRA124_CLK_DISP1, .present = true },
763 [tegra_clk_host1x_8] = { .dt_id = TEGRA124_CLK_HOST1X, .present = true },
764 [tegra_clk_vcp] = { .dt_id = TEGRA124_CLK_VCP, .present = true },
765 [tegra_clk_i2s0] = { .dt_id = TEGRA124_CLK_I2S0, .present = true },
766 [tegra_clk_apbdma] = { .dt_id = TEGRA124_CLK_APBDMA, .present = true },
767 [tegra_clk_kbc] = { .dt_id = TEGRA124_CLK_KBC, .present = true },
768 [tegra_clk_kfuse] = { .dt_id = TEGRA124_CLK_KFUSE, .present = true },
769 [tegra_clk_sbc1] = { .dt_id = TEGRA124_CLK_SBC1, .present = true },
770 [tegra_clk_nor] = { .dt_id = TEGRA124_CLK_NOR, .present = true },
771 [tegra_clk_sbc2] = { .dt_id = TEGRA124_CLK_SBC2, .present = true },
772 [tegra_clk_sbc3] = { .dt_id = TEGRA124_CLK_SBC3, .present = true },
773 [tegra_clk_i2c5] = { .dt_id = TEGRA124_CLK_I2C5, .present = true },
774 [tegra_clk_mipi] = { .dt_id = TEGRA124_CLK_MIPI, .present = true },
775 [tegra_clk_hdmi] = { .dt_id = TEGRA124_CLK_HDMI, .present = true },
776 [tegra_clk_csi] = { .dt_id = TEGRA124_CLK_CSI, .present = true },
777 [tegra_clk_i2c2] = { .dt_id = TEGRA124_CLK_I2C2, .present = true },
778 [tegra_clk_uartc] = { .dt_id = TEGRA124_CLK_UARTC, .present = true },
779 [tegra_clk_mipi_cal] = { .dt_id = TEGRA124_CLK_MIPI_CAL, .present = true },
780 [tegra_clk_usb2] = { .dt_id = TEGRA124_CLK_USB2, .present = true },
781 [tegra_clk_usb3] = { .dt_id = TEGRA124_CLK_USB3, .present = true },
782 [tegra_clk_vde_8] = { .dt_id = TEGRA124_CLK_VDE, .present = true },
783 [tegra_clk_bsea] = { .dt_id = TEGRA124_CLK_BSEA, .present = true },
784 [tegra_clk_bsev] = { .dt_id = TEGRA124_CLK_BSEV, .present = true },
785 [tegra_clk_uartd] = { .dt_id = TEGRA124_CLK_UARTD, .present = true },
786 [tegra_clk_i2c3] = { .dt_id = TEGRA124_CLK_I2C3, .present = true },
787 [tegra_clk_sbc4] = { .dt_id = TEGRA124_CLK_SBC4, .present = true },
788 [tegra_clk_sdmmc3_8] = { .dt_id = TEGRA124_CLK_SDMMC3, .present = true },
789 [tegra_clk_pcie] = { .dt_id = TEGRA124_CLK_PCIE, .present = true },
790 [tegra_clk_owr] = { .dt_id = TEGRA124_CLK_OWR, .present = true },
791 [tegra_clk_afi] = { .dt_id = TEGRA124_CLK_AFI, .present = true },
792 [tegra_clk_csite] = { .dt_id = TEGRA124_CLK_CSITE, .present = true },
793 [tegra_clk_la] = { .dt_id = TEGRA124_CLK_LA, .present = true },
794 [tegra_clk_trace] = { .dt_id = TEGRA124_CLK_TRACE, .present = true },
795 [tegra_clk_soc_therm] = { .dt_id = TEGRA124_CLK_SOC_THERM, .present = true },
796 [tegra_clk_dtv] = { .dt_id = TEGRA124_CLK_DTV, .present = true },
797 [tegra_clk_i2cslow] = { .dt_id = TEGRA124_CLK_I2CSLOW, .present = true },
798 [tegra_clk_tsec] = { .dt_id = TEGRA124_CLK_TSEC, .present = true },
799 [tegra_clk_xusb_host] = { .dt_id = TEGRA124_CLK_XUSB_HOST, .present = true },
800 [tegra_clk_msenc] = { .dt_id = TEGRA124_CLK_MSENC, .present = true },
801 [tegra_clk_csus] = { .dt_id = TEGRA124_CLK_CSUS, .present = true },
802 [tegra_clk_mselect] = { .dt_id = TEGRA124_CLK_MSELECT, .present = true },
803 [tegra_clk_tsensor] = { .dt_id = TEGRA124_CLK_TSENSOR, .present = true },
804 [tegra_clk_i2s3] = { .dt_id = TEGRA124_CLK_I2S3, .present = true },
805 [tegra_clk_i2s4] = { .dt_id = TEGRA124_CLK_I2S4, .present = true },
806 [tegra_clk_i2c4] = { .dt_id = TEGRA124_CLK_I2C4, .present = true },
807 [tegra_clk_sbc5] = { .dt_id = TEGRA124_CLK_SBC5, .present = true },
808 [tegra_clk_sbc6] = { .dt_id = TEGRA124_CLK_SBC6, .present = true },
809 [tegra_clk_d_audio] = { .dt_id = TEGRA124_CLK_D_AUDIO, .present = true },
810 [tegra_clk_apbif] = { .dt_id = TEGRA124_CLK_APBIF, .present = true },
811 [tegra_clk_dam0] = { .dt_id = TEGRA124_CLK_DAM0, .present = true },
812 [tegra_clk_dam1] = { .dt_id = TEGRA124_CLK_DAM1, .present = true },
813 [tegra_clk_dam2] = { .dt_id = TEGRA124_CLK_DAM2, .present = true },
814 [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA124_CLK_HDA2CODEC_2X, .present = true },
815 [tegra_clk_audio0_2x] = { .dt_id = TEGRA124_CLK_AUDIO0_2X, .present = true },
816 [tegra_clk_audio1_2x] = { .dt_id = TEGRA124_CLK_AUDIO1_2X, .present = true },
817 [tegra_clk_audio2_2x] = { .dt_id = TEGRA124_CLK_AUDIO2_2X, .present = true },
818 [tegra_clk_audio3_2x] = { .dt_id = TEGRA124_CLK_AUDIO3_2X, .present = true },
819 [tegra_clk_audio4_2x] = { .dt_id = TEGRA124_CLK_AUDIO4_2X, .present = true },
820 [tegra_clk_spdif_2x] = { .dt_id = TEGRA124_CLK_SPDIF_2X, .present = true },
821 [tegra_clk_actmon] = { .dt_id = TEGRA124_CLK_ACTMON, .present = true },
822 [tegra_clk_extern1] = { .dt_id = TEGRA124_CLK_EXTERN1, .present = true },
823 [tegra_clk_extern2] = { .dt_id = TEGRA124_CLK_EXTERN2, .present = true },
824 [tegra_clk_extern3] = { .dt_id = TEGRA124_CLK_EXTERN3, .present = true },
825 [tegra_clk_sata_oob] = { .dt_id = TEGRA124_CLK_SATA_OOB, .present = true },
826 [tegra_clk_sata] = { .dt_id = TEGRA124_CLK_SATA, .present = true },
827 [tegra_clk_hda] = { .dt_id = TEGRA124_CLK_HDA, .present = true },
828 [tegra_clk_se] = { .dt_id = TEGRA124_CLK_SE, .present = true },
829 [tegra_clk_hda2hdmi] = { .dt_id = TEGRA124_CLK_HDA2HDMI, .present = true },
830 [tegra_clk_sata_cold] = { .dt_id = TEGRA124_CLK_SATA_COLD, .present = true },
831 [tegra_clk_cilab] = { .dt_id = TEGRA124_CLK_CILAB, .present = true },
832 [tegra_clk_cilcd] = { .dt_id = TEGRA124_CLK_CILCD, .present = true },
833 [tegra_clk_cile] = { .dt_id = TEGRA124_CLK_CILE, .present = true },
834 [tegra_clk_dsialp] = { .dt_id = TEGRA124_CLK_DSIALP, .present = true },
835 [tegra_clk_dsiblp] = { .dt_id = TEGRA124_CLK_DSIBLP, .present = true },
836 [tegra_clk_entropy] = { .dt_id = TEGRA124_CLK_ENTROPY, .present = true },
837 [tegra_clk_dds] = { .dt_id = TEGRA124_CLK_DDS, .present = true },
838 [tegra_clk_dp2] = { .dt_id = TEGRA124_CLK_DP2, .present = true },
839 [tegra_clk_amx] = { .dt_id = TEGRA124_CLK_AMX, .present = true },
840 [tegra_clk_adx] = { .dt_id = TEGRA124_CLK_ADX, .present = true },
841 [tegra_clk_xusb_ss] = { .dt_id = TEGRA124_CLK_XUSB_SS, .present = true },
842 [tegra_clk_i2c6] = { .dt_id = TEGRA124_CLK_I2C6, .present = true },
843 [tegra_clk_vim2_clk] = { .dt_id = TEGRA124_CLK_VIM2_CLK, .present = true },
844 [tegra_clk_hdmi_audio] = { .dt_id = TEGRA124_CLK_HDMI_AUDIO, .present = true },
845 [tegra_clk_clk72Mhz] = { .dt_id = TEGRA124_CLK_CLK72MHZ, .present = true },
846 [tegra_clk_vic03] = { .dt_id = TEGRA124_CLK_VIC03, .present = true },
847 [tegra_clk_adx1] = { .dt_id = TEGRA124_CLK_ADX1, .present = true },
848 [tegra_clk_dpaux] = { .dt_id = TEGRA124_CLK_DPAUX, .present = true },
849 [tegra_clk_sor0] = { .dt_id = TEGRA124_CLK_SOR0, .present = true },
850 [tegra_clk_sor0_out] = { .dt_id = TEGRA124_CLK_SOR0_OUT, .present = true },
851 [tegra_clk_gpu] = { .dt_id = TEGRA124_CLK_GPU, .present = true },
852 [tegra_clk_amx1] = { .dt_id = TEGRA124_CLK_AMX1, .present = true },
853 [tegra_clk_uartb] = { .dt_id = TEGRA124_CLK_UARTB, .present = true },
854 [tegra_clk_vfir] = { .dt_id = TEGRA124_CLK_VFIR, .present = true },
855 [tegra_clk_spdif_in] = { .dt_id = TEGRA124_CLK_SPDIF_IN, .present = true },
856 [tegra_clk_spdif_out] = { .dt_id = TEGRA124_CLK_SPDIF_OUT, .present = true },
857 [tegra_clk_vi_9] = { .dt_id = TEGRA124_CLK_VI, .present = true },
858 [tegra_clk_vi_sensor_8] = { .dt_id = TEGRA124_CLK_VI_SENSOR, .present = true },
859 [tegra_clk_fuse] = { .dt_id = TEGRA124_CLK_FUSE, .present = true },
860 [tegra_clk_fuse_burn] = { .dt_id = TEGRA124_CLK_FUSE_BURN, .present = true },
861 [tegra_clk_clk_32k] = { .dt_id = TEGRA124_CLK_CLK_32K, .present = true },
862 [tegra_clk_clk_m] = { .dt_id = TEGRA124_CLK_CLK_M, .present = true },
863 [tegra_clk_osc] = { .dt_id = TEGRA124_CLK_OSC, .present = true },
864 [tegra_clk_osc_div2] = { .dt_id = TEGRA124_CLK_OSC_DIV2, .present = true },
865 [tegra_clk_osc_div4] = { .dt_id = TEGRA124_CLK_OSC_DIV4, .present = true },
866 [tegra_clk_pll_ref] = { .dt_id = TEGRA124_CLK_PLL_REF, .present = true },
867 [tegra_clk_pll_c] = { .dt_id = TEGRA124_CLK_PLL_C, .present = true },
868 [tegra_clk_pll_c_out1] = { .dt_id = TEGRA124_CLK_PLL_C_OUT1, .present = true },
869 [tegra_clk_pll_c2] = { .dt_id = TEGRA124_CLK_PLL_C2, .present = true },
870 [tegra_clk_pll_c3] = { .dt_id = TEGRA124_CLK_PLL_C3, .present = true },
871 [tegra_clk_pll_m] = { .dt_id = TEGRA124_CLK_PLL_M, .present = true },
872 [tegra_clk_pll_m_out1] = { .dt_id = TEGRA124_CLK_PLL_M_OUT1, .present = true },
873 [tegra_clk_pll_p] = { .dt_id = TEGRA124_CLK_PLL_P, .present = true },
874 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA124_CLK_PLL_P_OUT1, .present = true },
875 [tegra_clk_pll_p_out2] = { .dt_id = TEGRA124_CLK_PLL_P_OUT2, .present = true },
876 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA124_CLK_PLL_P_OUT3, .present = true },
877 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA124_CLK_PLL_P_OUT4, .present = true },
878 [tegra_clk_pll_a] = { .dt_id = TEGRA124_CLK_PLL_A, .present = true },
879 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA124_CLK_PLL_A_OUT0, .present = true },
880 [tegra_clk_pll_d] = { .dt_id = TEGRA124_CLK_PLL_D, .present = true },
881 [tegra_clk_pll_d_out0] = { .dt_id = TEGRA124_CLK_PLL_D_OUT0, .present = true },
882 [tegra_clk_pll_d2] = { .dt_id = TEGRA124_CLK_PLL_D2, .present = true },
883 [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA124_CLK_PLL_D2_OUT0, .present = true },
884 [tegra_clk_pll_u] = { .dt_id = TEGRA124_CLK_PLL_U, .present = true },
885 [tegra_clk_pll_u_480m] = { .dt_id = TEGRA124_CLK_PLL_U_480M, .present = true },
886 [tegra_clk_pll_u_60m] = { .dt_id = TEGRA124_CLK_PLL_U_60M, .present = true },
887 [tegra_clk_pll_u_48m] = { .dt_id = TEGRA124_CLK_PLL_U_48M, .present = true },
888 [tegra_clk_pll_u_12m] = { .dt_id = TEGRA124_CLK_PLL_U_12M, .present = true },
889 [tegra_clk_pll_x] = { .dt_id = TEGRA124_CLK_PLL_X, .present = true },
890 [tegra_clk_pll_x_out0] = { .dt_id = TEGRA124_CLK_PLL_X_OUT0, .present = true },
891 [tegra_clk_pll_re_vco] = { .dt_id = TEGRA124_CLK_PLL_RE_VCO, .present = true },
892 [tegra_clk_pll_re_out] = { .dt_id = TEGRA124_CLK_PLL_RE_OUT, .present = true },
893 [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA124_CLK_SPDIF_IN_SYNC, .present = true },
894 [tegra_clk_i2s0_sync] = { .dt_id = TEGRA124_CLK_I2S0_SYNC, .present = true },
895 [tegra_clk_i2s1_sync] = { .dt_id = TEGRA124_CLK_I2S1_SYNC, .present = true },
896 [tegra_clk_i2s2_sync] = { .dt_id = TEGRA124_CLK_I2S2_SYNC, .present = true },
897 [tegra_clk_i2s3_sync] = { .dt_id = TEGRA124_CLK_I2S3_SYNC, .present = true },
898 [tegra_clk_i2s4_sync] = { .dt_id = TEGRA124_CLK_I2S4_SYNC, .present = true },
899 [tegra_clk_vimclk_sync] = { .dt_id = TEGRA124_CLK_VIMCLK_SYNC, .present = true },
900 [tegra_clk_audio0] = { .dt_id = TEGRA124_CLK_AUDIO0, .present = true },
901 [tegra_clk_audio1] = { .dt_id = TEGRA124_CLK_AUDIO1, .present = true },
902 [tegra_clk_audio2] = { .dt_id = TEGRA124_CLK_AUDIO2, .present = true },
903 [tegra_clk_audio3] = { .dt_id = TEGRA124_CLK_AUDIO3, .present = true },
904 [tegra_clk_audio4] = { .dt_id = TEGRA124_CLK_AUDIO4, .present = true },
905 [tegra_clk_spdif] = { .dt_id = TEGRA124_CLK_SPDIF, .present = true },
906 [tegra_clk_xusb_host_src] = { .dt_id = TEGRA124_CLK_XUSB_HOST_SRC, .present = true },
907 [tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA124_CLK_XUSB_FALCON_SRC, .present = true },
908 [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA124_CLK_XUSB_FS_SRC, .present = true },
909 [tegra_clk_xusb_ss_src] = { .dt_id = TEGRA124_CLK_XUSB_SS_SRC, .present = true },
910 [tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA124_CLK_XUSB_SS_DIV2, .present = true },
911 [tegra_clk_xusb_dev_src] = { .dt_id = TEGRA124_CLK_XUSB_DEV_SRC, .present = true },
912 [tegra_clk_xusb_dev] = { .dt_id = TEGRA124_CLK_XUSB_DEV, .present = true },
913 [tegra_clk_xusb_hs_src] = { .dt_id = TEGRA124_CLK_XUSB_HS_SRC, .present = true },
914 [tegra_clk_sclk] = { .dt_id = TEGRA124_CLK_SCLK, .present = true },
915 [tegra_clk_hclk] = { .dt_id = TEGRA124_CLK_HCLK, .present = true },
916 [tegra_clk_pclk] = { .dt_id = TEGRA124_CLK_PCLK, .present = true },
917 [tegra_clk_cclk_g] = { .dt_id = TEGRA124_CLK_CCLK_G, .present = true },
918 [tegra_clk_cclk_lp] = { .dt_id = TEGRA124_CLK_CCLK_LP, .present = true },
919 [tegra_clk_dfll_ref] = { .dt_id = TEGRA124_CLK_DFLL_REF, .present = true },
920 [tegra_clk_dfll_soc] = { .dt_id = TEGRA124_CLK_DFLL_SOC, .present = true },
921 [tegra_clk_vi_sensor2] = { .dt_id = TEGRA124_CLK_VI_SENSOR2, .present = true },
922 [tegra_clk_pll_p_out5] = { .dt_id = TEGRA124_CLK_PLL_P_OUT5, .present = true },
923 [tegra_clk_pll_c4] = { .dt_id = TEGRA124_CLK_PLL_C4, .present = true },
924 [tegra_clk_pll_dp] = { .dt_id = TEGRA124_CLK_PLL_DP, .present = true },
925 [tegra_clk_audio0_mux] = { .dt_id = TEGRA124_CLK_AUDIO0_MUX, .present = true },
926 [tegra_clk_audio1_mux] = { .dt_id = TEGRA124_CLK_AUDIO1_MUX, .present = true },
927 [tegra_clk_audio2_mux] = { .dt_id = TEGRA124_CLK_AUDIO2_MUX, .present = true },
928 [tegra_clk_audio3_mux] = { .dt_id = TEGRA124_CLK_AUDIO3_MUX, .present = true },
929 [tegra_clk_audio4_mux] = { .dt_id = TEGRA124_CLK_AUDIO4_MUX, .present = true },
930 [tegra_clk_spdif_mux] = { .dt_id = TEGRA124_CLK_SPDIF_MUX, .present = true },
931 [tegra_clk_cec] = { .dt_id = TEGRA124_CLK_CEC, .present = true },
1588 tegra124_clks[tegra_clk_cclk_g].present = false;
1589 tegra124_clks[tegra_clk_cclk_lp].present = false;
1590 tegra124_clks[tegra_clk_pll_x].present = false;
1591 tegra124_clks[tegra_clk_pll_x_out0].present = false;