Lines Matching defs:data
137 struct tegra_audio_clk_initdata *data;
140 for (i = 0, data = sync; i < num_sync_clks; i++, data++) {
141 dt_clk = tegra_lookup_dt_id(data->mux_clk_id, tegra_clks);
145 clk = clk_register_mux(NULL, data->mux_name, mux_names,
148 clk_base + data->offset, 0, 3, 0,
152 dt_clk = tegra_lookup_dt_id(data->gate_clk_id, tegra_clks);
156 clk = clk_register_gate(NULL, data->gate_name, data->mux_name,
157 0, clk_base + data->offset, 4,
173 pr_err("No audio data passed to tegra_audio_clk_init\n");
203 struct tegra_sync_source_initdata *data;
205 data = &sync_source_clks[i];
207 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
211 clk = tegra_clk_register_sync_source(data->name, sync_max_rate);
228 struct tegra_audio2x_clk_initdata *data;
230 data = &audio2x_clks[i];
231 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
235 clk = clk_register_fixed_factor(NULL, data->name_2x,
236 data->parent, CLK_SET_RATE_PARENT, 2, 1);
237 clk = tegra_clk_register_divider(data->div_name,
238 data->name_2x, clk_base + AUDIO_SYNC_DOUBLER,
239 0, 0, data->div_offset, 1, 0,
241 clk = tegra_clk_register_periph_gate(data->gate_name,
242 data->div_name, TEGRA_PERIPH_NO_RESET,
243 clk_base, CLK_SET_RATE_PARENT, data->clk_num,