clk/tegra/clk-super.c

83 	 * For LP mode super-clock switch between PLLX direct
148 	struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
149 	struct clk_hw *div_hw = &super->frac_div.hw;
154 	rate = super->div_ops->round_rate(div_hw, req->rate,
166 	struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
167 	struct clk_hw *div_hw = &super->frac_div.hw;
171 	return super->div_ops->recalc_rate(div_hw, parent_rate);
177 	struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
178 	struct clk_hw *div_hw = &super->frac_div.hw;
182 	return super->div_ops->set_rate(div_hw, rate, parent_rate);
187 	struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
188 	struct clk_hw *div_hw = &super->frac_div.hw;
195 	super->div_ops->restore_context(div_hw);
213 	struct tegra_clk_super_mux *super;
217 	super = kzalloc(sizeof(*super), GFP_KERNEL);
218 	if (!super)
227 	super->reg = reg;
228 	super->pllx_index = pllx_index;
229 	super->div2_index = div2_index;
230 	super->lock = lock;
231 	super->width = width;
232 	super->flags = clk_super_flags;
235 	super->hw.init = &init;
237 	clk = tegra_clk_dev_register(&super->hw);
239 		kfree(super);
249 	struct tegra_clk_super_mux *super;
253 	super = kzalloc(sizeof(*super), GFP_KERNEL);
254 	if (!super)
263 	super->reg = reg;
264 	super->lock = lock;
265 	super->width = 4;
266 	super->flags = clk_super_flags;
267 	super->frac_div.reg = reg + 4;
268 	super->frac_div.shift = 16;
269 	super->frac_div.width = 8;
270 	super->frac_div.frac_width = 1;
271 	super->frac_div.lock = lock;
272 	super->div_ops = &tegra_clk_frac_div_ops;
275 	super->hw.init = &init;
277 	clk = clk_register(NULL, &super->hw);
279 		kfree(super);