clk/tegra/clk-pll.c

237 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
238 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
239 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
240 #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset)
241 #define pll_writel_sdm_din(val, p) pll_writel(val, p->params->sdm_din_reg, p)
242 #define pll_writel_sdm_ctrl(val, p) pll_writel(val, p->params->sdm_ctrl_reg, p)
278 	u32 val;
286 	val = pll_readl_misc(pll);
287 	val |= BIT(pll->params->lock_enable_bit_idx);
288 	pll_writel_misc(val, pll);
294 	u32 val, lock_mask;
311 		val = readl_relaxed(lock_addr);
312 		if ((val & lock_mask) == lock_mask) {
332 	u32 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
334 	return (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) &&
335 	      !(val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE);
341 	u32 val;
351 	val = pll_readl_base(pll);
353 	return val & PLL_BASE_ENABLE ? 1 : 0;
359 	u32 val;
362 		val = pll_readl(pll->params->iddq_reg, pll);
363 		val &= ~BIT(pll->params->iddq_bit_idx);
364 		pll_writel(val, pll->params->iddq_reg, pll);
369 		val = pll_readl(pll->params->reset_reg, pll);
370 		val &= ~BIT(pll->params->reset_bit_idx);
371 		pll_writel(val, pll->params->reset_reg, pll);
376 	val = pll_readl_base(pll);
378 		val &= ~PLL_BASE_BYPASS;
379 	val |= PLL_BASE_ENABLE;
380 	pll_writel_base(val, pll);
383 		val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
384 		val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
385 		writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
392 	u32 val;
394 	val = pll_readl_base(pll);
396 		val &= ~PLL_BASE_BYPASS;
397 	val &= ~PLL_BASE_ENABLE;
398 	pll_writel_base(val, pll);
401 		val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);
402 		val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;
403 		writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
407 		val = pll_readl(pll->params->reset_reg, pll);
408 		val |= BIT(pll->params->reset_bit_idx);
409 		pll_writel(val, pll->params->reset_reg, pll);
413 		val = pll_readl(pll->params->iddq_reg, pll);
414 		val |= BIT(pll->params->iddq_bit_idx);
415 		pll_writel(val, pll->params->iddq_reg, pll);
423 		u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
425 		val |= pll->params->ssc_ctrl_en_mask;
426 		pll_writel(val, pll->params->ssc_ctrl_reg, pll);
433 		u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll);
435 		val &= ~pll->params->ssc_ctrl_en_mask;
436 		pll_writel(val, pll->params->ssc_ctrl_reg, pll);
631 	u32 val;
638 		val = pll_readl_sdm_din(pll) & (~sdm_din_mask(pll));
639 		val |= sdin_data_to_din(cfg->sdm_data) & sdm_din_mask(pll);
640 		pll_writel_sdm_din(val, pll);
643 	val = pll_readl_sdm_ctrl(pll);
644 	enabled = (val & sdm_en_mask(pll));
647 		val &= ~pll->params->sdm_ctrl_en_mask;
650 		val |= pll->params->sdm_ctrl_en_mask;
652 	pll_writel_sdm_ctrl(val, pll);
658 	u32 val;
665 		val = pll_override_readl(params->pmc_divp_reg, pll);
666 		val &= ~(divp_mask(pll) << div_nmp->override_divp_shift);
667 		val |= cfg->p << div_nmp->override_divp_shift;
668 		pll_override_writel(val, params->pmc_divp_reg, pll);
670 		val = pll_override_readl(params->pmc_divnm_reg, pll);
671 		val &= ~((divm_mask(pll) << div_nmp->override_divm_shift) |
673 		val |= (cfg->m << div_nmp->override_divm_shift) |
675 		pll_override_writel(val, params->pmc_divnm_reg, pll);
677 		val = pll_readl_base(pll);
679 		val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) |
682 		val |= (cfg->m << divm_shift(pll)) |
686 		pll_writel_base(val, pll);
695 	u32 val;
704 		val = pll_override_readl(params->pmc_divp_reg, pll);
705 		cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll);
707 		val = pll_override_readl(params->pmc_divnm_reg, pll);
708 		cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll);
709 		cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll);
711 		val = pll_readl_base(pll);
713 		cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll);
714 		cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll);
715 		cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll);
719 				val = pll_readl_sdm_din(pll);
720 				val &= sdm_din_mask(pll);
721 				cfg->sdm_data = sdin_din_to_data(val);
731 	u32 val;
733 	val = pll_readl_misc(pll);
735 	val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);
736 	val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;
739 		val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);
741 			val |= 1 << PLL_MISC_LFCON_SHIFT;
743 		val &= ~(1 << PLL_MISC_DCCON_SHIFT);
745 			val |= 1 << PLL_MISC_DCCON_SHIFT;
748 	pll_writel_misc(val, pll);
868 	u32 val;
872 	val = pll_readl_base(pll);
874 	if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))
879 			!(val & PLL_BASE_OVERRIDE)) {
916 	u32 val;
926 	val = readl(pll->pmc + PMC_SATA_PWRGT);
927 	val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
928 	writel(val, pll->pmc + PMC_SATA_PWRGT);
930 	val = readl(pll->pmc + PMC_SATA_PWRGT);
931 	val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;
932 	writel(val, pll->pmc + PMC_SATA_PWRGT);
934 	val = readl(pll->pmc + PMC_SATA_PWRGT);
935 	val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;
936 	writel(val, pll->pmc + PMC_SATA_PWRGT);
938 	val = pll_readl_misc(pll);
942 		val = pll_readl_misc(pll);
943 		if (val & PLLE_MISC_READY)
960 	u32 val;
973 	val = pll_readl_misc(pll);
974 	val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
975 	pll_writel_misc(val, pll);
977 	val = pll_readl_misc(pll);
978 	if (!(val & PLLE_MISC_READY)) {
986 		val = pll_readl_base(pll);
987 		val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
989 		val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
990 		val |= sel.m << divm_shift(pll);
991 		val |= sel.n << divn_shift(pll);
992 		val |= sel.p << divp_shift(pll);
993 		val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
994 		pll_writel_base(val, pll);
997 	val = pll_readl_misc(pll);
998 	val |= PLLE_MISC_SETUP_VALUE;
999 	val |= PLLE_MISC_LOCK_ENABLE;
1000 	pll_writel_misc(val, pll);
1002 	val = readl(pll->clk_base + PLLE_SS_CTRL);
1003 	val &= ~PLLE_SS_COEFFICIENTS_MASK;
1004 	val |= PLLE_SS_DISABLE;
1005 	writel(val, pll->clk_base + PLLE_SS_CTRL);
1007 	val = pll_readl_base(pll);
1008 	val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);
1009 	pll_writel_base(val, pll);
1020 	u32 val = pll_readl_base(pll);
1024 	divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll));
1025 	divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll));
1026 	divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll));
1271 	u32 val;
1296 	val = step_a << pll_params->stepa_shift;
1297 	val |= step_b << pll_params->stepb_shift;
1298 	writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);
1383 	u32 val;
1385 	val = pll_readl_misc(pll);
1386 	val |= PLLCX_MISC_STROBE;
1387 	pll_writel_misc(val, pll);
1390 	val &= ~PLLCX_MISC_STROBE;
1391 	pll_writel_misc(val, pll);
1397 	u32 val;
1410 	val = pll_readl_misc(pll);
1411 	val &= ~PLLCX_MISC_RESET;
1412 	pll_writel_misc(val, pll);
1428 	u32 val;
1432 	val = pll_readl_misc(pll);
1433 	val |= PLLCX_MISC_RESET;
1434 	pll_writel_misc(val, pll);
1455 	u32 val, n_threshold;
1477 	val = pll_readl_misc(pll);
1478 	val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK);
1479 	val |= n <= n_threshold ?
1481 	pll_writel_misc(val, pll);
1613 	u32 val;
1626 	val = pll_readl_base(pll);
1627 	val &= ~BIT(29); /* Disable lock override */
1628 	pll_writel_base(val, pll);
1630 	val = pll_readl(pll->params->aux_reg, pll);
1631 	val |= PLLE_AUX_ENABLE_SWCTL;
1632 	val &= ~PLLE_AUX_SEQ_ENABLE;
1633 	pll_writel(val, pll->params->aux_reg, pll);
1636 	val = pll_readl_misc(pll);
1637 	val |= PLLE_MISC_LOCK_ENABLE;
1638 	val |= PLLE_MISC_IDDQ_SW_CTRL;
1639 	val &= ~PLLE_MISC_IDDQ_SW_VALUE;
1640 	val |= PLLE_MISC_PLLE_PTS;
1641 	val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK);
1642 	pll_writel_misc(val, pll);
1645 	val = pll_readl(PLLE_SS_CTRL, pll);
1646 	val |= PLLE_SS_DISABLE;
1647 	pll_writel(val, PLLE_SS_CTRL, pll);
1649 	val = pll_readl_base(pll);
1650 	val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
1652 	val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
1653 	val |= sel.m << divm_shift(pll);
1654 	val |= sel.n << divn_shift(pll);
1655 	val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
1656 	pll_writel_base(val, pll);
1665 	val = pll_readl(PLLE_SS_CTRL, pll);
1666 	val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
1667 	val &= ~PLLE_SS_COEFFICIENTS_MASK;
1668 	val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA114;
1669 	pll_writel(val, PLLE_SS_CTRL, pll);
1670 	val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
1671 	pll_writel(val, PLLE_SS_CTRL, pll);
1673 	val &= ~PLLE_SS_CNTL_INTERP_RESET;
1674 	pll_writel(val, PLLE_SS_CTRL, pll);
1678 	val = pll_readl_misc(pll);
1679 	val &= ~PLLE_MISC_IDDQ_SW_CTRL;
1680 	pll_writel_misc(val, pll);
1682 	val = pll_readl(pll->params->aux_reg, pll);
1683 	val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE);
1684 	val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
1685 	pll_writel(val, pll->params->aux_reg, pll);
1687 	val |= PLLE_AUX_SEQ_ENABLE;
1688 	pll_writel(val, pll->params->aux_reg, pll);
1690 	val = pll_readl(XUSBIO_PLL_CFG0, pll);
1691 	val |= (XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET |
1693 	val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL |
1695 	pll_writel(val, XUSBIO_PLL_CFG0, pll);
1697 	val |= XUSBIO_PLL_CFG0_SEQ_ENABLE;
1698 	pll_writel(val, XUSBIO_PLL_CFG0, pll);
1701 	val = pll_readl(SATA_PLL_CFG0, pll);
1702 	val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;
1703 	val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET;
1704 	val |= SATA_PLL_CFG0_SEQ_START_STATE;
1705 	pll_writel(val, SATA_PLL_CFG0, pll);
1709 	val = pll_readl(SATA_PLL_CFG0, pll);
1710 	val |= SATA_PLL_CFG0_SEQ_ENABLE;
1711 	pll_writel(val, SATA_PLL_CFG0, pll);
1724 	u32 val;
1731 	val = pll_readl_misc(pll);
1732 	val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
1733 	pll_writel_misc(val, pll);
1849 	u32 val, val_aux;
1852 	val = pll_readl_base(pll);
1855 	if (val & PLL_BASE_ENABLE) {
2051 	u32 val, val_iddq;
2082 		val = readl_relaxed(clk_base + pll_params->base_reg);
2085 		if (val & PLL_BASE_ENABLE)
2112 	u32 val;
2128 	val = pll_readl_base(pll);
2129 	if (val & PLL_BASE_ENABLE)
2136 		val = m << divm_shift(pll);
2137 		val |= (pll_params->vco_min / parent_rate) << divn_shift(pll);
2138 		pll_writel_base(val, pll);
2143 	val = pll_readl_misc(pll);
2144 	val &= ~BIT(29);
2145 	pll_writel_misc(val, pll);
2338 	u32 val, val_iddq;
2355 	val = pll_readl_base(pll);
2356 	val &= ~PLLSS_REF_SRC_SEL_MASK;
2357 	pll_writel_base(val, pll);
2384 	val = pll_readl_base(pll);
2386 	if (val & PLL_BASE_ENABLE) {
2397 	val &= ~PLLSS_LOCK_OVERRIDE;
2398 	pll_writel_base(val, pll);
2441 	u32 val;
2443 	val = pll_readl_base(pll);
2445 	return val & PLLE_BASE_ENABLE ? 1 : 0;
2452 	u32 val;
2468 	val = pll_readl(pll->params->aux_reg, pll);
2469 	if (val & PLLE_AUX_SEQ_ENABLE)
2472 	val = pll_readl_base(pll);
2473 	val &= ~BIT(30); /* Disable lock override */
2474 	pll_writel_base(val, pll);
2476 	val = pll_readl_misc(pll);
2477 	val |= PLLE_MISC_LOCK_ENABLE;
2478 	val |= PLLE_MISC_IDDQ_SW_CTRL;
2479 	val &= ~PLLE_MISC_IDDQ_SW_VALUE;
2480 	val |= PLLE_MISC_PLLE_PTS;
2481 	val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK);
2482 	pll_writel_misc(val, pll);
2485 	val = pll_readl(PLLE_SS_CTRL, pll);
2486 	val |= PLLE_SS_DISABLE;
2487 	pll_writel(val, PLLE_SS_CTRL, pll);
2489 	val = pll_readl_base(pll);
2490 	val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |
2492 	val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);
2493 	val |= sel.m << divm_shift(pll);
2494 	val |= sel.n << divn_shift(pll);
2495 	val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;
2496 	pll_writel_base(val, pll);
2499 	val = pll_readl_base(pll);
2500 	val |= PLLE_BASE_ENABLE;
2501 	pll_writel_base(val, pll);
2508 	val = pll_readl(PLLE_SS_CTRL, pll);
2509 	val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);
2510 	val &= ~PLLE_SS_COEFFICIENTS_MASK;
2511 	val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA210;
2512 	pll_writel(val, PLLE_SS_CTRL, pll);
2513 	val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);
2514 	pll_writel(val, PLLE_SS_CTRL, pll);
2516 	val &= ~PLLE_SS_CNTL_INTERP_RESET;
2517 	pll_writel(val, PLLE_SS_CTRL, pll);
2531 	u32 val;
2537 	val = pll_readl(pll->params->aux_reg, pll);
2538 	if (val & PLLE_AUX_SEQ_ENABLE)
2541 	val = pll_readl_base(pll);
2542 	val &= ~PLLE_BASE_ENABLE;
2543 	pll_writel_base(val, pll);
2545 	val = pll_readl(pll->params->aux_reg, pll);
2546 	val |= PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL;
2547 	pll_writel(val, pll->params->aux_reg, pll);
2549 	val = pll_readl_misc(pll);
2550 	val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;
2551 	pll_writel_misc(val, pll);
2648 	u32 val;
2660 	val = readl_relaxed(clk_base + pll_params->base_reg);
2661 	if (val & PLLSS_REF_SRC_SEL_MASK) {