Lines Matching defs:input_rate
526 for (sel = pll->params->freq_table; sel->input_rate != 0; sel++)
527 if (sel->input_rate == parent_rate &&
531 if (sel->input_rate == 0)
542 cfg->input_rate = sel->input_rate;
959 unsigned long input_rate;
966 input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
968 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
1122 unsigned long flags = 0, input_rate;
1132 input_rate = clk_hw_get_rate(osc);
1145 if (input_rate == utmi_parameters[i].osc_frequency) {
1153 input_rate);
1235 cfg->input_rate = parent_rate;
1254 u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate)
1258 return (u16)_pll_fixed_mdiv(pll->params, input_rate);
1453 unsigned long input_rate, u32 n)
1457 switch (input_rate) {
1473 __func__, input_rate);
1616 unsigned long input_rate;
1618 input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
1620 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
1745 unsigned long flags = 0, input_rate;
1755 input_rate = clk_hw_get_rate(__clk_get_hw(osc));
1768 if (input_rate == utmi_parameters[i].osc_frequency) {
1776 input_rate);
2455 unsigned long input_rate;
2460 input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
2462 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))