Lines Matching refs:common
41 .common = {
57 .common = {
71 .common = {
80 &pll_periph0_4x_clk.common.hw
88 &pll_periph0_2x_clk.common.hw
109 .common = {
118 &pll_video0_4x_clk.common.hw
133 .common = {
142 &pll_video1_4x_clk.common.hw
156 .common = {
184 .common = {
194 &pll_audio0_4x_clk.common.hw
213 .common = {
222 &pll_audio1_clk.common.hw
237 { .hw = &pll_cpux_clk.common.hw },
239 { .hw = &pll_periph0_2x_clk.common.hw },
240 { .hw = &pll_periph0_800M_clk.common.hw },
245 static const struct clk_hw *cpux_hws[] = { &cpux_clk.common.hw };
266 { .hw = &psi_ahb_clk.common.hw },
281 static const struct clk_hw *psi_ahb_hws[] = { &psi_ahb_clk.common.hw };
282 static const struct clk_hw *apb0_hws[] = { &apb0_clk.common.hw };
283 static const struct clk_hw *apb1_hws[] = { &apb1_clk.common.hw };
286 &pll_periph0_2x_clk.common.hw,
287 &pll_video0_4x_clk.common.hw,
288 &pll_video1_4x_clk.common.hw,
289 &pll_audio1_div2_clk.common.hw,
320 { .hw = &pll_periph0_2x_clk.common.hw },
334 &pll_ve_clk.common.hw,
335 &pll_periph0_2x_clk.common.hw,
375 &pll_ddr0_clk.common.hw,
376 &pll_audio1_div2_clk.common.hw,
377 &pll_periph0_2x_clk.common.hw,
378 &pll_periph0_800M_clk.common.hw,
387 &dram_clk.common.hw, 4, 1, 0);
412 { .hw = &pll_periph0_2x_clk.common.hw },
413 { .hw = &pll_audio1_div2_clk.common.hw },
432 { .hw = &pll_periph0_2x_clk.common.hw },
433 { .hw = &pll_periph0_800M_clk.common.hw },
434 { .hw = &pll_audio1_div2_clk.common.hw },
480 { .hw = &pll_periph0_2x_clk.common.hw },
481 { .hw = &pll_audio1_div2_clk.common.hw },
482 { .hw = &pll_audio1_div5_clk.common.hw },
531 &pll_audio0_4x_clk.common.hw,
532 &pll_audio1_div2_clk.common.hw,
533 &pll_audio1_div5_clk.common.hw,
557 &pll_audio0_4x_clk.common.hw,
559 &pll_audio1_div2_clk.common.hw,
560 &pll_audio1_div5_clk.common.hw,
585 &pll_audio1_div2_clk.common.hw,
586 &pll_audio1_div5_clk.common.hw,
600 &pll_audio1_div2_clk.common.hw,
601 &pll_audio1_div5_clk.common.hw,
654 .common = {
672 .common = {
708 { .hw = &hdmi_cec_32k_clk.common.hw },
723 { .hw = &pll_audio1_div2_clk.common.hw },
736 &pll_video0_4x_clk.common.hw,
738 &pll_video1_4x_clk.common.hw,
739 &pll_periph0_2x_clk.common.hw,
740 &pll_audio1_div2_clk.common.hw,
802 &pll_periph0_2x_clk.common.hw,
817 { .hw = &pll_audio1_div2_clk.common.hw },
818 { .hw = &pll_audio1_div5_clk.common.hw },
848 { .hw = &pll_periph0_2x_clk.common.hw },
849 { .hw = &pll_audio1_div2_clk.common.hw },
868 { .hw = &pll_periph0_800M_clk.common.hw },
870 { .hw = &pll_cpux_clk.common.hw },
871 { .hw = &pll_audio1_div2_clk.common.hw },
885 static SUNXI_CCU_DIV_TABLE_HW(riscv_axi_clk, "riscv-axi", &riscv_clk.common.hw,
920 &fanout_32k_clk.common.hw,
921 &fanout_12M_clk.common.hw,
922 &fanout_16M_clk.common.hw,
923 &fanout_24M_clk.common.hw,
924 &fanout_25M_clk.common.hw,
925 &fanout_27M_clk.common.hw,
926 &fanout_pclk_clk.common.hw,
942 &pll_cpux_clk.common,
943 &pll_ddr0_clk.common,
944 &pll_periph0_4x_clk.common,
945 &pll_periph0_2x_clk.common,
946 &pll_periph0_800M_clk.common,
947 &pll_video0_4x_clk.common,
948 &pll_video1_4x_clk.common,
949 &pll_ve_clk.common,
950 &pll_audio0_4x_clk.common,
951 &pll_audio1_clk.common,
952 &pll_audio1_div2_clk.common,
953 &pll_audio1_div5_clk.common,
954 &cpux_clk.common,
955 &cpux_axi_clk.common,
956 &cpux_apb_clk.common,
957 &psi_ahb_clk.common,
958 &apb0_clk.common,
959 &apb1_clk.common,
960 &de_clk.common,
961 &bus_de_clk.common,
962 &di_clk.common,
963 &bus_di_clk.common,
964 &g2d_clk.common,
965 &bus_g2d_clk.common,
966 &ce_clk.common,
967 &bus_ce_clk.common,
968 &ve_clk.common,
969 &bus_ve_clk.common,
970 &bus_dma_clk.common,
971 &bus_msgbox0_clk.common,
972 &bus_msgbox1_clk.common,
973 &bus_msgbox2_clk.common,
974 &bus_spinlock_clk.common,
975 &bus_hstimer_clk.common,
976 &avs_clk.common,
977 &bus_dbg_clk.common,
978 &bus_pwm_clk.common,
979 &bus_iommu_clk.common,
980 &dram_clk.common,
981 &mbus_dma_clk.common,
982 &mbus_ve_clk.common,
983 &mbus_ce_clk.common,
984 &mbus_tvin_clk.common,
985 &mbus_csi_clk.common,
986 &mbus_g2d_clk.common,
987 &mbus_riscv_clk.common,
988 &bus_dram_clk.common,
989 &mmc0_clk.common,
990 &mmc1_clk.common,
991 &mmc2_clk.common,
992 &bus_mmc0_clk.common,
993 &bus_mmc1_clk.common,
994 &bus_mmc2_clk.common,
995 &bus_uart0_clk.common,
996 &bus_uart1_clk.common,
997 &bus_uart2_clk.common,
998 &bus_uart3_clk.common,
999 &bus_uart4_clk.common,
1000 &bus_uart5_clk.common,
1001 &bus_i2c0_clk.common,
1002 &bus_i2c1_clk.common,
1003 &bus_i2c2_clk.common,
1004 &bus_i2c3_clk.common,
1005 &bus_can0_clk.common,
1006 &bus_can1_clk.common,
1007 &spi0_clk.common,
1008 &spi1_clk.common,
1009 &bus_spi0_clk.common,
1010 &bus_spi1_clk.common,
1011 &emac_25M_clk.common,
1012 &bus_emac_clk.common,
1013 &ir_tx_clk.common,
1014 &bus_ir_tx_clk.common,
1015 &bus_gpadc_clk.common,
1016 &bus_ths_clk.common,
1017 &i2s0_clk.common,
1018 &i2s1_clk.common,
1019 &i2s2_clk.common,
1020 &i2s2_asrc_clk.common,
1021 &bus_i2s0_clk.common,
1022 &bus_i2s1_clk.common,
1023 &bus_i2s2_clk.common,
1024 &spdif_tx_clk.common,
1025 &spdif_rx_clk.common,
1026 &bus_spdif_clk.common,
1027 &dmic_clk.common,
1028 &bus_dmic_clk.common,
1029 &audio_dac_clk.common,
1030 &audio_adc_clk.common,
1031 &bus_audio_clk.common,
1032 &usb_ohci0_clk.common,
1033 &usb_ohci1_clk.common,
1034 &bus_ohci0_clk.common,
1035 &bus_ohci1_clk.common,
1036 &bus_ehci0_clk.common,
1037 &bus_ehci1_clk.common,
1038 &bus_otg_clk.common,
1039 &bus_lradc_clk.common,
1040 &bus_dpss_top_clk.common,
1041 &hdmi_24M_clk.common,
1042 &hdmi_cec_32k_clk.common,
1043 &hdmi_cec_clk.common,
1044 &bus_hdmi_clk.common,
1045 &mipi_dsi_clk.common,
1046 &bus_mipi_dsi_clk.common,
1047 &tcon_lcd0_clk.common,
1048 &bus_tcon_lcd0_clk.common,
1049 &tcon_tv_clk.common,
1050 &bus_tcon_tv_clk.common,
1051 &tve_clk.common,
1052 &bus_tve_top_clk.common,
1053 &bus_tve_clk.common,
1054 &tvd_clk.common,
1055 &bus_tvd_top_clk.common,
1056 &bus_tvd_clk.common,
1057 &ledc_clk.common,
1058 &bus_ledc_clk.common,
1059 &csi_top_clk.common,
1060 &csi_mclk_clk.common,
1061 &bus_csi_clk.common,
1062 &tpadc_clk.common,
1063 &bus_tpadc_clk.common,
1064 &bus_tzma_clk.common,
1065 &dsp_clk.common,
1066 &bus_dsp_cfg_clk.common,
1067 &riscv_clk.common,
1068 &riscv_axi_clk.common,
1069 &bus_riscv_cfg_clk.common,
1070 &fanout_24M_clk.common,
1071 &fanout_12M_clk.common,
1072 &fanout_16M_clk.common,
1073 &fanout_25M_clk.common,
1074 &fanout_32k_clk.common,
1075 &fanout_27M_clk.common,
1076 &fanout_pclk_clk.common,
1077 &fanout0_clk.common,
1078 &fanout1_clk.common,
1079 &fanout2_clk.common,
1085 [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw,
1086 [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
1087 [CLK_PLL_PERIPH0_4X] = &pll_periph0_4x_clk.common.hw,
1088 [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.common.hw,
1089 [CLK_PLL_PERIPH0_800M] = &pll_periph0_800M_clk.common.hw,
1092 [CLK_PLL_VIDEO0_4X] = &pll_video0_4x_clk.common.hw,
1095 [CLK_PLL_VIDEO1_4X] = &pll_video1_4x_clk.common.hw,
1098 [CLK_PLL_VE] = &pll_ve_clk.common.hw,
1099 [CLK_PLL_AUDIO0_4X] = &pll_audio0_4x_clk.common.hw,
1102 [CLK_PLL_AUDIO1] = &pll_audio1_clk.common.hw,
1103 [CLK_PLL_AUDIO1_DIV2] = &pll_audio1_div2_clk.common.hw,
1104 [CLK_PLL_AUDIO1_DIV5] = &pll_audio1_div5_clk.common.hw,
1105 [CLK_CPUX] = &cpux_clk.common.hw,
1106 [CLK_CPUX_AXI] = &cpux_axi_clk.common.hw,
1107 [CLK_CPUX_APB] = &cpux_apb_clk.common.hw,
1108 [CLK_PSI_AHB] = &psi_ahb_clk.common.hw,
1109 [CLK_APB0] = &apb0_clk.common.hw,
1110 [CLK_APB1] = &apb1_clk.common.hw,
1112 [CLK_DE] = &de_clk.common.hw,
1113 [CLK_BUS_DE] = &bus_de_clk.common.hw,
1114 [CLK_DI] = &di_clk.common.hw,
1115 [CLK_BUS_DI] = &bus_di_clk.common.hw,
1116 [CLK_G2D] = &g2d_clk.common.hw,
1117 [CLK_BUS_G2D] = &bus_g2d_clk.common.hw,
1118 [CLK_CE] = &ce_clk.common.hw,
1119 [CLK_BUS_CE] = &bus_ce_clk.common.hw,
1120 [CLK_VE] = &ve_clk.common.hw,
1121 [CLK_BUS_VE] = &bus_ve_clk.common.hw,
1122 [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
1123 [CLK_BUS_MSGBOX0] = &bus_msgbox0_clk.common.hw,
1124 [CLK_BUS_MSGBOX1] = &bus_msgbox1_clk.common.hw,
1125 [CLK_BUS_MSGBOX2] = &bus_msgbox2_clk.common.hw,
1126 [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
1127 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
1128 [CLK_AVS] = &avs_clk.common.hw,
1129 [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
1130 [CLK_BUS_PWM] = &bus_pwm_clk.common.hw,
1131 [CLK_BUS_IOMMU] = &bus_iommu_clk.common.hw,
1132 [CLK_DRAM] = &dram_clk.common.hw,
1133 [CLK_MBUS_DMA] = &mbus_dma_clk.common.hw,
1134 [CLK_MBUS_VE] = &mbus_ve_clk.common.hw,
1135 [CLK_MBUS_CE] = &mbus_ce_clk.common.hw,
1136 [CLK_MBUS_TVIN] = &mbus_tvin_clk.common.hw,
1137 [CLK_MBUS_CSI] = &mbus_csi_clk.common.hw,
1138 [CLK_MBUS_G2D] = &mbus_g2d_clk.common.hw,
1139 [CLK_MBUS_RISCV] = &mbus_riscv_clk.common.hw,
1140 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
1141 [CLK_MMC0] = &mmc0_clk.common.hw,
1142 [CLK_MMC1] = &mmc1_clk.common.hw,
1143 [CLK_MMC2] = &mmc2_clk.common.hw,
1144 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
1145 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
1146 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
1147 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
1148 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
1149 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
1150 [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
1151 [CLK_BUS_UART4] = &bus_uart4_clk.common.hw,
1152 [CLK_BUS_UART5] = &bus_uart5_clk.common.hw,
1153 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
1154 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
1155 [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
1156 [CLK_BUS_I2C3] = &bus_i2c3_clk.common.hw,
1157 [CLK_BUS_CAN0] = &bus_can0_clk.common.hw,
1158 [CLK_BUS_CAN1] = &bus_can1_clk.common.hw,
1159 [CLK_SPI0] = &spi0_clk.common.hw,
1160 [CLK_SPI1] = &spi1_clk.common.hw,
1161 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
1162 [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
1163 [CLK_EMAC_25M] = &emac_25M_clk.common.hw,
1164 [CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
1165 [CLK_IR_TX] = &ir_tx_clk.common.hw,
1166 [CLK_BUS_IR_TX] = &bus_ir_tx_clk.common.hw,
1167 [CLK_BUS_GPADC] = &bus_gpadc_clk.common.hw,
1168 [CLK_BUS_THS] = &bus_ths_clk.common.hw,
1169 [CLK_I2S0] = &i2s0_clk.common.hw,
1170 [CLK_I2S1] = &i2s1_clk.common.hw,
1171 [CLK_I2S2] = &i2s2_clk.common.hw,
1172 [CLK_I2S2_ASRC] = &i2s2_asrc_clk.common.hw,
1173 [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
1174 [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
1175 [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw,
1176 [CLK_SPDIF_TX] = &spdif_tx_clk.common.hw,
1177 [CLK_SPDIF_RX] = &spdif_rx_clk.common.hw,
1178 [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
1179 [CLK_DMIC] = &dmic_clk.common.hw,
1180 [CLK_BUS_DMIC] = &bus_dmic_clk.common.hw,
1181 [CLK_AUDIO_DAC] = &audio_dac_clk.common.hw,
1182 [CLK_AUDIO_ADC] = &audio_adc_clk.common.hw,
1183 [CLK_BUS_AUDIO] = &bus_audio_clk.common.hw,
1184 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
1185 [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
1186 [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
1187 [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw,
1188 [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
1189 [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw,
1190 [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
1191 [CLK_BUS_LRADC] = &bus_lradc_clk.common.hw,
1192 [CLK_BUS_DPSS_TOP] = &bus_dpss_top_clk.common.hw,
1193 [CLK_HDMI_24M] = &hdmi_24M_clk.common.hw,
1194 [CLK_HDMI_CEC_32K] = &hdmi_cec_32k_clk.common.hw,
1195 [CLK_HDMI_CEC] = &hdmi_cec_clk.common.hw,
1196 [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw,
1197 [CLK_MIPI_DSI] = &mipi_dsi_clk.common.hw,
1198 [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw,
1199 [CLK_TCON_LCD0] = &tcon_lcd0_clk.common.hw,
1200 [CLK_BUS_TCON_LCD0] = &bus_tcon_lcd0_clk.common.hw,
1201 [CLK_TCON_TV] = &tcon_tv_clk.common.hw,
1202 [CLK_BUS_TCON_TV] = &bus_tcon_tv_clk.common.hw,
1203 [CLK_TVE] = &tve_clk.common.hw,
1204 [CLK_BUS_TVE_TOP] = &bus_tve_top_clk.common.hw,
1205 [CLK_BUS_TVE] = &bus_tve_clk.common.hw,
1206 [CLK_TVD] = &tvd_clk.common.hw,
1207 [CLK_BUS_TVD_TOP] = &bus_tvd_top_clk.common.hw,
1208 [CLK_BUS_TVD] = &bus_tvd_clk.common.hw,
1209 [CLK_LEDC] = &ledc_clk.common.hw,
1210 [CLK_BUS_LEDC] = &bus_ledc_clk.common.hw,
1211 [CLK_CSI_TOP] = &csi_top_clk.common.hw,
1212 [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw,
1213 [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
1214 [CLK_TPADC] = &tpadc_clk.common.hw,
1215 [CLK_BUS_TPADC] = &bus_tpadc_clk.common.hw,
1216 [CLK_BUS_TZMA] = &bus_tzma_clk.common.hw,
1217 [CLK_DSP] = &dsp_clk.common.hw,
1218 [CLK_BUS_DSP_CFG] = &bus_dsp_cfg_clk.common.hw,
1219 [CLK_RISCV] = &riscv_clk.common.hw,
1220 [CLK_RISCV_AXI] = &riscv_axi_clk.common.hw,
1221 [CLK_BUS_RISCV_CFG] = &bus_riscv_cfg_clk.common.hw,
1222 [CLK_FANOUT_24M] = &fanout_24M_clk.common.hw,
1223 [CLK_FANOUT_12M] = &fanout_12M_clk.common.hw,
1224 [CLK_FANOUT_16M] = &fanout_16M_clk.common.hw,
1225 [CLK_FANOUT_25M] = &fanout_25M_clk.common.hw,
1226 [CLK_FANOUT_32K] = &fanout_32k_clk.common.hw,
1227 [CLK_FANOUT_27M] = &fanout_27M_clk.common.hw,
1228 [CLK_FANOUT_PCLK] = &fanout_pclk_clk.common.hw,
1229 [CLK_FANOUT0] = &fanout0_clk.common.hw,
1230 [CLK_FANOUT1] = &fanout1_clk.common.hw,
1231 [CLK_FANOUT2] = &fanout2_clk.common.hw,
1333 .common = &riscv_clk.common,
1387 ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,