Lines Matching defs:output
315 static int clk_pll3200c32_get_params(unsigned long input, unsigned long output,
329 if (output < 800000000 || output > 1600000000)
333 output /= 1000;
336 n = i * output / (2 * input);
346 new_deviation = abs(new_freq - output);
462 /* PLL output structure
463 * FVCO >> /2 >> FVCOBY2 (no output)
466 * FVCOby2 output = (input * 2 * NDIV) / IDF (assuming FRAC_CONTROL==L)
471 * 19.05Mhz <= FVCOby2 output (PHI w ODF=1) <= 3000Mhz
476 static int clk_pll4600c28_get_params(unsigned long input, unsigned long output,
485 if (output < 19000000 || output > 3000000000u)
495 n = output / (infin * 2);
503 if (new_freq < output)
506 new_deviation = new_freq - output;
801 "clock-output-names",