Lines Matching refs:hw
30 /* some pll clocks configure CLK_IGNORE_UNUSED because hw dvfs does not call
31 * clock interface. hw dvfs can not gate the pll clock.
83 [CLK_26M_AUD] = &clk_26m_aud.hw,
84 [CLK_13M] = &clk_13m.hw,
85 [CLK_6M5] = &clk_6m5.hw,
86 [CLK_4M3] = &clk_4m3.hw,
87 [CLK_2M] = &clk_2m.hw,
88 [CLK_1M] = &clk_1m.hw,
89 [CLK_250K] = &clk_250k.hw,
90 [CLK_RCO_25M] = &rco_25m.hw,
91 [CLK_RCO_4M] = &rco_4m.hw,
92 [CLK_RCO_2M] = &rco_2m.hw,
93 [CLK_ISPPLL_GATE] = &isppll_gate.common.hw,
94 [CLK_DPLL0_GATE] = &dpll0_gate.common.hw,
95 [CLK_DPLL1_GATE] = &dpll1_gate.common.hw,
96 [CLK_LPLL_GATE] = &lpll_gate.common.hw,
97 [CLK_TWPLL_GATE] = &twpll_gate.common.hw,
98 [CLK_GPLL_GATE] = &gpll_gate.common.hw,
99 [CLK_RPLL_GATE] = &rpll_gate.common.hw,
100 [CLK_CPPLL_GATE] = &cppll_gate.common.hw,
101 [CLK_MPLL0_GATE] = &mpll0_gate.common.hw,
102 [CLK_MPLL1_GATE] = &mpll1_gate.common.hw,
103 [CLK_MPLL2_GATE] = &mpll2_gate.common.hw,
132 static SPRD_PLL_HW(dpll0, "dpll0", &dpll0_gate.common.hw, 0x4, 3,
134 static CLK_FIXED_FACTOR_HW(dpll0_58m31, "dpll0-58m31", &dpll0.common.hw,
144 [CLK_DPLL0] = &dpll0.common.hw,
145 [CLK_DPLL0_58M31] = &dpll0_58m31.hw,
175 static SPRD_PLL_HW(mpll1, "mpll1", &mpll1_gate.common.hw, 0x0, 3,
177 static CLK_FIXED_FACTOR_HW(mpll1_63m38, "mpll1-63m38", &mpll1.common.hw,
187 [CLK_MPLL1] = &mpll1.common.hw,
188 [CLK_MPLL1_63M38] = &mpll1_63m38.hw,
238 static SPRD_PLL_HW(mpll0, "mpll0", &mpll0_gate.common.hw, 0x54, 3,
240 static CLK_FIXED_FACTOR_HW(mpll0_56m88, "mpll0-56m88", &mpll0.common.hw,
248 static SPRD_PLL_HW(mpll2, "mpll2", &mpll2_gate.common.hw, 0x9c, 3,
250 static CLK_FIXED_FACTOR_HW(mpll2_47m13, "mpll2-47m13", &mpll2.common.hw,
263 [CLK_RPLL] = &rpll.common.hw,
264 [CLK_AUDIO_GATE] = &audio_gate.common.hw,
265 [CLK_MPLL0] = &mpll0.common.hw,
266 [CLK_MPLL0_56M88] = &mpll0_56m88.hw,
267 [CLK_MPLL2] = &mpll2.common.hw,
268 [CLK_MPLL2_47M13] = &mpll2_47m13.hw,
282 static CLK_FIXED_FACTOR_HW(twpll_768m, "twpll-768m", &twpll.common.hw,
284 static CLK_FIXED_FACTOR_HW(twpll_384m, "twpll-384m", &twpll.common.hw,
286 static CLK_FIXED_FACTOR_HW(twpll_192m, "twpll-192m", &twpll.common.hw,
288 static CLK_FIXED_FACTOR_HW(twpll_96m, "twpll-96m", &twpll.common.hw,
290 static CLK_FIXED_FACTOR_HW(twpll_48m, "twpll-48m", &twpll.common.hw,
292 static CLK_FIXED_FACTOR_HW(twpll_24m, "twpll-24m", &twpll.common.hw,
294 static CLK_FIXED_FACTOR_HW(twpll_12m, "twpll-12m", &twpll.common.hw,
296 static CLK_FIXED_FACTOR_HW(twpll_512m, "twpll-512m", &twpll.common.hw,
298 static CLK_FIXED_FACTOR_HW(twpll_256m, "twpll-256m", &twpll.common.hw,
300 static CLK_FIXED_FACTOR_HW(twpll_128m, "twpll-128m", &twpll.common.hw,
302 static CLK_FIXED_FACTOR_HW(twpll_64m, "twpll-64m", &twpll.common.hw,
304 static CLK_FIXED_FACTOR_HW(twpll_307m2, "twpll-307m2", &twpll.common.hw,
306 static CLK_FIXED_FACTOR_HW(twpll_219m4, "twpll-219m4", &twpll.common.hw,
308 static CLK_FIXED_FACTOR_HW(twpll_170m6, "twpll-170m6", &twpll.common.hw,
310 static CLK_FIXED_FACTOR_HW(twpll_153m6, "twpll-153m6", &twpll.common.hw,
312 static CLK_FIXED_FACTOR_HW(twpll_76m8, "twpll-76m8", &twpll.common.hw,
314 static CLK_FIXED_FACTOR_HW(twpll_51m2, "twpll-51m2", &twpll.common.hw,
316 static CLK_FIXED_FACTOR_HW(twpll_38m4, "twpll-38m4", &twpll.common.hw,
318 static CLK_FIXED_FACTOR_HW(twpll_19m2, "twpll-19m2", &twpll.common.hw,
320 static CLK_FIXED_FACTOR_HW(twpll_12m29, "twpll-12m29", &twpll.common.hw,
325 static CLK_FIXED_FACTOR_HW(lpll_614m4, "lpll-614m4", &lpll.common.hw,
327 static CLK_FIXED_FACTOR_HW(lpll_409m6, "lpll-409m6", &lpll.common.hw,
329 static CLK_FIXED_FACTOR_HW(lpll_245m76, "lpll-245m76", &lpll.common.hw,
331 static CLK_FIXED_FACTOR_HW(lpll_30m72, "lpll-30m72", &lpll.common.hw,
336 static CLK_FIXED_FACTOR_HW(isppll_468m, "isppll-468m", &isppll.common.hw,
338 static CLK_FIXED_FACTOR_HW(isppll_78m, "isppll-78m", &isppll.common.hw,
341 static SPRD_PLL_HW(gpll, "gpll", &gpll_gate.common.hw, 0x48, 3,
343 static CLK_FIXED_FACTOR_HW(gpll_40m, "gpll-40m", &gpll.common.hw,
346 static SPRD_PLL_HW(cppll, "cppll", &cppll_gate.common.hw, 0x60, 3,
348 static CLK_FIXED_FACTOR_HW(cppll_39m32, "cppll-39m32", &cppll.common.hw,
362 [CLK_TWPLL] = &twpll.common.hw,
363 [CLK_TWPLL_768M] = &twpll_768m.hw,
364 [CLK_TWPLL_384M] = &twpll_384m.hw,
365 [CLK_TWPLL_192M] = &twpll_192m.hw,
366 [CLK_TWPLL_96M] = &twpll_96m.hw,
367 [CLK_TWPLL_48M] = &twpll_48m.hw,
368 [CLK_TWPLL_24M] = &twpll_24m.hw,
369 [CLK_TWPLL_12M] = &twpll_12m.hw,
370 [CLK_TWPLL_512M] = &twpll_512m.hw,
371 [CLK_TWPLL_256M] = &twpll_256m.hw,
372 [CLK_TWPLL_128M] = &twpll_128m.hw,
373 [CLK_TWPLL_64M] = &twpll_64m.hw,
374 [CLK_TWPLL_307M2] = &twpll_307m2.hw,
375 [CLK_TWPLL_219M4] = &twpll_219m4.hw,
376 [CLK_TWPLL_170M6] = &twpll_170m6.hw,
377 [CLK_TWPLL_153M6] = &twpll_153m6.hw,
378 [CLK_TWPLL_76M8] = &twpll_76m8.hw,
379 [CLK_TWPLL_51M2] = &twpll_51m2.hw,
380 [CLK_TWPLL_38M4] = &twpll_38m4.hw,
381 [CLK_TWPLL_19M2] = &twpll_19m2.hw,
382 [CLK_TWPLL_12M29] = &twpll_12m29.hw,
383 [CLK_LPLL] = &lpll.common.hw,
384 [CLK_LPLL_614M4] = &lpll_614m4.hw,
385 [CLK_LPLL_409M6] = &lpll_409m6.hw,
386 [CLK_LPLL_245M76] = &lpll_245m76.hw,
387 [CLK_LPLL_30M72] = &lpll_30m72.hw,
388 [CLK_ISPPLL] = &isppll.common.hw,
389 [CLK_ISPPLL_468M] = &isppll_468m.hw,
390 [CLK_ISPPLL_78M] = &isppll_78m.hw,
391 [CLK_GPLL] = &gpll.common.hw,
392 [CLK_GPLL_40M] = &gpll_40m.hw,
393 [CLK_CPPLL] = &cppll.common.hw,
394 [CLK_CPPLL_39M32] = &cppll_39m32.hw,
440 [CLK_DSI_EB] = &dsi_eb.common.hw,
441 [CLK_DISPC_EB] = &dispc_eb.common.hw,
442 [CLK_VSP_EB] = &vsp_eb.common.hw,
443 [CLK_VDMA_EB] = &vdma_eb.common.hw,
444 [CLK_DMA_PUB_EB] = &dma_pub_eb.common.hw,
445 [CLK_DMA_SEC_EB] = &dma_sec_eb.common.hw,
446 [CLK_IPI_EB] = &ipi_eb.common.hw,
447 [CLK_AHB_CKG_EB] = &ahb_ckg_eb.common.hw,
448 [CLK_BM_CLK_EB] = &bm_clk_eb.common.hw,
462 { .hw = &twpll_64m.hw },
463 { .hw = &twpll_96m.hw },
464 { .hw = &twpll_128m.hw },
471 { .hw = &twpll_64m.hw },
472 { .hw = &twpll_96m.hw },
473 { .hw = &twpll_128m.hw },
480 { .hw = &twpll_48m.hw },
481 { .hw = &twpll_51m2.hw },
482 { .hw = &twpll_96m.hw },
493 { .hw = &twpll_48m.hw },
494 { .hw = &twpll_51m2.hw },
495 { .hw = &twpll_153m6.hw },
510 { .hw = &twpll_128m.hw },
511 { .hw = &twpll_153m6.hw },
512 { .hw = &twpll_192m.hw },
525 { .hw = &twpll_128m.hw },
526 { .hw = &twpll_153m6.hw },
537 { .hw = &twpll_51m2.hw },
538 { .hw = &twpll_64m.hw },
539 { .hw = &twpll_96m.hw },
540 { .hw = &twpll_128m.hw },
547 { .hw = &twpll_96m.hw },
548 { .hw = &twpll_192m.hw },
549 { .hw = &twpll_256m.hw },
555 { .hw = &clk_1m.hw },
557 { .hw = &twpll_307m2.hw },
558 { .hw = &twpll_384m.hw },
559 { .hw = &rpll.common.hw },
560 { .hw = &lpll_409m6.hw },
570 { .hw = &twpll_256m.hw },
571 { .hw = &twpll_307m2.hw },
572 { .hw = &twpll_384m.hw },
578 { .hw = &twpll_153m6.hw },
579 { .hw = &twpll_192m.hw },
580 { .hw = &twpll_256m.hw },
581 { .hw = &twpll_307m2.hw },
582 { .hw = &twpll_384m.hw },
588 { .hw = &twpll_96m.hw },
589 { .hw = &twpll_128m.hw },
590 { .hw = &twpll_153m6.hw },
591 { .hw = &twpll_192m.hw },
597 { .hw = &twpll_96m.hw },
598 { .hw = &twpll_128m.hw },
599 { .hw = &twpll_153m6.hw },
600 { .hw = &twpll_192m.hw },
612 { .hw = &twpll_256m.hw },
613 { .hw = &twpll_384m.hw },
614 { .hw = &twpll_512m.hw },
615 { .hw = &lpll_614m4.hw },
616 { .hw = &twpll_768m.hw },
617 { .hw = &isppll.common.hw },
621 static SPRD_DIV_CLK_HW(vdsp_m_clk, "vdsp-m-clk", &vdsp_clk.common.hw,
661 [CLK_AP_APB] = &ap_apb_clk.common.hw,
662 [CLK_IPI] = &ipi_clk.common.hw,
663 [CLK_AP_UART0] = &ap_uart0_clk.common.hw,
664 [CLK_AP_UART1] = &ap_uart1_clk.common.hw,
665 [CLK_AP_UART2] = &ap_uart2_clk.common.hw,
666 [CLK_AP_I2C0] = &ap_i2c0_clk.common.hw,
667 [CLK_AP_I2C1] = &ap_i2c1_clk.common.hw,
668 [CLK_AP_I2C2] = &ap_i2c2_clk.common.hw,
669 [CLK_AP_I2C3] = &ap_i2c3_clk.common.hw,
670 [CLK_AP_I2C4] = &ap_i2c4_clk.common.hw,
671 [CLK_AP_SPI0] = &ap_spi0_clk.common.hw,
672 [CLK_AP_SPI1] = &ap_spi1_clk.common.hw,
673 [CLK_AP_SPI2] = &ap_spi2_clk.common.hw,
674 [CLK_AP_SPI3] = &ap_spi3_clk.common.hw,
675 [CLK_AP_IIS0] = &ap_iis0_clk.common.hw,
676 [CLK_AP_IIS1] = &ap_iis1_clk.common.hw,
677 [CLK_AP_IIS2] = &ap_iis2_clk.common.hw,
678 [CLK_AP_SIM] = &ap_sim_clk.common.hw,
679 [CLK_AP_CE] = &ap_ce_clk.common.hw,
680 [CLK_SDIO0_2X] = &sdio0_2x_clk.common.hw,
681 [CLK_SDIO1_2X] = &sdio1_2x_clk.common.hw,
682 [CLK_EMMC_2X] = &emmc_2x_clk.common.hw,
683 [CLK_VSP] = &vsp_clk.common.hw,
684 [CLK_DISPC0] = &dispc0_clk.common.hw,
685 [CLK_DISPC0_DPI] = &dispc0_dpi_clk.common.hw,
686 [CLK_DSI_APB] = &dsi_apb_clk.common.hw,
687 [CLK_DSI_RXESC] = &dsi_rxesc.common.hw,
688 [CLK_DSI_LANEBYTE] = &dsi_lanebyte.common.hw,
689 [CLK_VDSP] = &vdsp_clk.common.hw,
690 [CLK_VDSP_M] = &vdsp_m_clk.common.hw,
703 { .hw = &rco_4m.hw },
705 { .hw = &clk_13m.hw },
706 { .hw = &rco_25m.hw },
708 { .hw = &twpll_96m.hw },
710 { .hw = &twpll_128m.hw },
717 { .hw = &rco_4m.hw },
719 { .hw = &rco_25m.hw },
720 { .hw = &twpll_38m4.hw },
721 { .hw = &twpll_51m2.hw },
729 { .hw = &clk_26m_aud.hw },
730 { .hw = &rco_25m.hw },
731 { .hw = &cppll_39m32.hw },
732 { .hw = &mpll0_56m88.hw },
733 { .hw = &mpll1_63m38.hw },
734 { .hw = &mpll2_47m13.hw },
735 { .hw = &dpll0_58m31.hw },
736 { .hw = &gpll_40m.hw },
737 { .hw = &twpll_48m.hw },
742 { .hw = &clk_26m_aud.hw },
743 { .hw = &rco_25m.hw },
744 { .hw = &cppll_39m32.hw },
745 { .hw = &mpll0_56m88.hw },
746 { .hw = &mpll1_63m38.hw },
747 { .hw = &mpll2_47m13.hw },
748 { .hw = &dpll0_58m31.hw },
749 { .hw = &gpll_40m.hw },
750 { .hw = &twpll_19m2.hw },
751 { .hw = &lpll_30m72.hw },
752 { .hw = &rpll.common.hw },
753 { .hw = &twpll_12m29.hw },
768 { .hw = &rco_4m.hw },
769 { .hw = &rco_25m.hw },
770 { .hw = &twpll_48m.hw },
782 { .hw = &rco_25m.hw },
789 { .hw = &rco_4m.hw },
791 { .hw = &twpll_48m.hw },
792 { .hw = &twpll_51m2.hw },
793 { .hw = &twpll_96m.hw },
795 { .hw = &twpll_128m.hw },
804 { .hw = &clk_250k.hw },
816 { .hw = &rco_4m.hw },
818 { .hw = &twpll_48m.hw },
819 { .hw = &twpll_51m2.hw },
821 { .hw = &twpll_153m6.hw },
828 { .hw = &twpll_128m.hw },
829 { .hw = &twpll_153m6.hw },
836 { .hw = &twpll_48m.hw },
837 { .hw = &twpll_51m2.hw },
838 { .hw = &twpll_96m.hw },
845 { .hw = &rco_4m.hw },
846 { .hw = &twpll_76m8.hw },
848 { .hw = &twpll_128m.hw },
849 { .hw = &twpll_153m6.hw },
860 { .hw = &twpll_128m.hw },
861 { .hw = &twpll_153m6.hw },
868 { .hw = &twpll_76m8.hw },
869 { .hw = &twpll_128m.hw },
870 { .hw = &twpll_192m.hw },
879 { .hw = &rco_4m.hw },
885 static SPRD_GATE_CLK_FW_NAME(djtag_tck_hw, "djtag-tck-hw", "ext-26m",
889 { .hw = &rco_4m.hw },
890 { .hw = &rco_25m.hw },
898 { .hw = &rco_4m.hw },
906 { .hw = &rco_4m.hw },
907 { .hw = &rco_25m.hw },
915 { .hw = &twpll_76m8.hw },
917 { .hw = &twpll_128m.hw },
924 { .hw = &twpll_96m.hw },
926 { .hw = &twpll_128m.hw },
935 { .hw = &twpll_12m.hw },
942 { .hw = &rco_25m.hw },
945 { .hw = &twpll_153m6.hw },
946 { .hw = &twpll_384m.hw },
947 { .hw = &twpll_512m.hw },
951 static SPRD_DIV_CLK_HW(cssys_pub_clk, "cssys-pub-clk", &cssys_clk.common.hw,
953 static SPRD_DIV_CLK_HW(cssys_apb_clk, "cssys-apb-clk", &cssys_clk.common.hw,
958 { .hw = &twpll_76m8.hw },
959 { .hw = &twpll_128m.hw },
960 { .hw = &twpll_256m.hw },
967 { .hw = &twpll_96m.hw },
968 { .hw = &twpll_128m.hw },
969 { .hw = &twpll_153m6.hw },
975 { .hw = &clk_1m.hw },
977 { .hw = &twpll_307m2.hw },
978 { .hw = &twpll_384m.hw },
979 { .hw = &rpll.common.hw },
980 { .hw = &lpll_409m6.hw },
987 { .hw = &twpll_48m.hw },
993 { .hw = &clk_6m5.hw },
994 { .hw = &clk_13m.hw },
1002 { .hw = &twpll_384m.hw },
1003 { .hw = &twpll_512m.hw },
1004 { .hw = &twpll_768m.hw },
1010 { .hw = &rco_25m.hw },
1012 { .hw = &twpll_192m.hw },
1013 { .hw = &twpll_96m.hw },
1015 { .hw = &twpll_128m.hw },
1021 { .hw = &rco_25m.hw },
1078 [CLK_AON_APB] = &aon_apb_clk.common.hw,
1079 [CLK_ADI] = &adi_clk.common.hw,
1080 [CLK_AUX0] = &aux0_clk.common.hw,
1081 [CLK_AUX1] = &aux1_clk.common.hw,
1082 [CLK_AUX2] = &aux2_clk.common.hw,
1083 [CLK_PROBE] = &probe_clk.common.hw,
1084 [CLK_PWM0] = &pwm0_clk.common.hw,
1085 [CLK_PWM1] = &pwm1_clk.common.hw,
1086 [CLK_PWM2] = &pwm2_clk.common.hw,
1087 [CLK_PWM3] = &pwm3_clk.common.hw,
1088 [CLK_EFUSE] = &efuse_clk.common.hw,
1089 [CLK_UART0] = &uart0_clk.common.hw,
1090 [CLK_UART1] = &uart1_clk.common.hw,
1091 [CLK_THM0] = &thm0_clk.common.hw,
1092 [CLK_THM1] = &thm1_clk.common.hw,
1093 [CLK_THM2] = &thm2_clk.common.hw,
1094 [CLK_THM3] = &thm3_clk.common.hw,
1095 [CLK_AON_I2C] = &aon_i2c_clk.common.hw,
1096 [CLK_AON_IIS] = &aon_iis_clk.common.hw,
1097 [CLK_SCC] = &scc_clk.common.hw,
1098 [CLK_APCPU_DAP] = &apcpu_dap_clk.common.hw,
1099 [CLK_APCPU_DAP_MTCK] = &apcpu_dap_mtck.common.hw,
1100 [CLK_APCPU_TS] = &apcpu_ts_clk.common.hw,
1101 [CLK_DEBUG_TS] = &debug_ts_clk.common.hw,
1102 [CLK_DSI_TEST_S] = &dsi_test_s.common.hw,
1103 [CLK_DJTAG_TCK] = &djtag_tck_clk.common.hw,
1104 [CLK_DJTAG_TCK_HW] = &djtag_tck_hw.common.hw,
1105 [CLK_AON_TMR] = &aon_tmr_clk.common.hw,
1106 [CLK_AON_PMU] = &aon_pmu_clk.common.hw,
1107 [CLK_DEBOUNCE] = &debounce_clk.common.hw,
1108 [CLK_APCPU_PMU] = &apcpu_pmu_clk.common.hw,
1109 [CLK_TOP_DVFS] = &top_dvfs_clk.common.hw,
1110 [CLK_OTG_UTMI] = &otg_utmi.common.hw,
1111 [CLK_OTG_REF] = &otg_ref_clk.common.hw,
1112 [CLK_CSSYS] = &cssys_clk.common.hw,
1113 [CLK_CSSYS_PUB] = &cssys_pub_clk.common.hw,
1114 [CLK_CSSYS_APB] = &cssys_apb_clk.common.hw,
1115 [CLK_AP_AXI] = &ap_axi_clk.common.hw,
1116 [CLK_AP_MM] = &ap_mm_clk.common.hw,
1117 [CLK_SDIO2_2X] = &sdio2_2x_clk.common.hw,
1118 [CLK_ANALOG_IO_APB] = &analog_io_apb.common.hw,
1119 [CLK_DMC_REF_CLK] = &dmc_ref_clk.common.hw,
1120 [CLK_EMC] = &emc_clk.common.hw,
1121 [CLK_USB] = &usb_clk.common.hw,
1122 [CLK_26M_PMU] = &pmu_26m_clk.common.hw,
1441 [CLK_RC100M_CAL_EB] = &rc100m_cal_eb.common.hw,
1442 [CLK_DJTAG_TCK_EB] = &djtag_tck_eb.common.hw,
1443 [CLK_DJTAG_EB] = &djtag_eb.common.hw,
1444 [CLK_AUX0_EB] = &aux0_eb.common.hw,
1445 [CLK_AUX1_EB] = &aux1_eb.common.hw,
1446 [CLK_AUX2_EB] = &aux2_eb.common.hw,
1447 [CLK_PROBE_EB] = &probe_eb.common.hw,
1448 [CLK_MM_EB] = &mm_eb.common.hw,
1449 [CLK_GPU_EB] = &gpu_eb.common.hw,
1450 [CLK_MSPI_EB] = &mspi_eb.common.hw,
1451 [CLK_APCPU_DAP_EB] = &apcpu_dap_eb.common.hw,
1452 [CLK_AON_CSSYS_EB] = &aon_cssys_eb.common.hw,
1453 [CLK_CSSYS_APB_EB] = &cssys_apb_eb.common.hw,
1454 [CLK_CSSYS_PUB_EB] = &cssys_pub_eb.common.hw,
1455 [CLK_SDPHY_CFG_EB] = &sdphy_cfg_eb.common.hw,
1456 [CLK_SDPHY_REF_EB] = &sdphy_ref_eb.common.hw,
1457 [CLK_EFUSE_EB] = &efuse_eb.common.hw,
1458 [CLK_GPIO_EB] = &gpio_eb.common.hw,
1459 [CLK_MBOX_EB] = &mbox_eb.common.hw,
1460 [CLK_KPD_EB] = &kpd_eb.common.hw,
1461 [CLK_AON_SYST_EB] = &aon_syst_eb.common.hw,
1462 [CLK_AP_SYST_EB] = &ap_syst_eb.common.hw,
1463 [CLK_AON_TMR_EB] = &aon_tmr_eb.common.hw,
1464 [CLK_OTG_UTMI_EB] = &otg_utmi_eb.common.hw,
1465 [CLK_OTG_PHY_EB] = &otg_phy_eb.common.hw,
1466 [CLK_SPLK_EB] = &splk_eb.common.hw,
1467 [CLK_PIN_EB] = &pin_eb.common.hw,
1468 [CLK_ANA_EB] = &ana_eb.common.hw,
1469 [CLK_APCPU_TS0_EB] = &apcpu_ts0_eb.common.hw,
1470 [CLK_APB_BUSMON_EB] = &apb_busmon_eb.common.hw,
1471 [CLK_AON_IIS_EB] = &aon_iis_eb.common.hw,
1472 [CLK_SCC_EB] = &scc_eb.common.hw,
1473 [CLK_THM0_EB] = &thm0_eb.common.hw,
1474 [CLK_THM1_EB] = &thm1_eb.common.hw,
1475 [CLK_THM2_EB] = &thm2_eb.common.hw,
1476 [CLK_ASIM_TOP_EB] = &asim_top_eb.common.hw,
1477 [CLK_I2C_EB] = &i2c_eb.common.hw,
1478 [CLK_PMU_EB] = &pmu_eb.common.hw,
1479 [CLK_ADI_EB] = &adi_eb.common.hw,
1480 [CLK_EIC_EB] = &eic_eb.common.hw,
1481 [CLK_AP_INTC0_EB] = &ap_intc0_eb.common.hw,
1482 [CLK_AP_INTC1_EB] = &ap_intc1_eb.common.hw,
1483 [CLK_AP_INTC2_EB] = &ap_intc2_eb.common.hw,
1484 [CLK_AP_INTC3_EB] = &ap_intc3_eb.common.hw,
1485 [CLK_AP_INTC4_EB] = &ap_intc4_eb.common.hw,
1486 [CLK_AP_INTC5_EB] = &ap_intc5_eb.common.hw,
1487 [CLK_AUDCP_INTC_EB] = &audcp_intc_eb.common.hw,
1488 [CLK_AP_TMR0_EB] = &ap_tmr0_eb.common.hw,
1489 [CLK_AP_TMR1_EB] = &ap_tmr1_eb.common.hw,
1490 [CLK_AP_TMR2_EB] = &ap_tmr2_eb.common.hw,
1491 [CLK_PWM0_EB] = &pwm0_eb.common.hw,
1492 [CLK_PWM1_EB] = &pwm1_eb.common.hw,
1493 [CLK_PWM2_EB] = &pwm2_eb.common.hw,
1494 [CLK_PWM3_EB] = &pwm3_eb.common.hw,
1495 [CLK_AP_WDG_EB] = &ap_wdg_eb.common.hw,
1496 [CLK_APCPU_WDG_EB] = &apcpu_wdg_eb.common.hw,
1497 [CLK_SERDES_EB] = &serdes_eb.common.hw,
1498 [CLK_ARCH_RTC_EB] = &arch_rtc_eb.common.hw,
1499 [CLK_KPD_RTC_EB] = &kpd_rtc_eb.common.hw,
1500 [CLK_AON_SYST_RTC_EB] = &aon_syst_rtc_eb.common.hw,
1501 [CLK_AP_SYST_RTC_EB] = &ap_syst_rtc_eb.common.hw,
1502 [CLK_AON_TMR_RTC_EB] = &aon_tmr_rtc_eb.common.hw,
1503 [CLK_EIC_RTC_EB] = &eic_rtc_eb.common.hw,
1504 [CLK_EIC_RTCDV5_EB] = &eic_rtcdv5_eb.common.hw,
1505 [CLK_AP_WDG_RTC_EB] = &ap_wdg_rtc_eb.common.hw,
1506 [CLK_AC_WDG_RTC_EB] = &ac_wdg_rtc_eb.common.hw,
1507 [CLK_AP_TMR0_RTC_EB] = &ap_tmr0_rtc_eb.common.hw,
1508 [CLK_AP_TMR1_RTC_EB] = &ap_tmr1_rtc_eb.common.hw,
1509 [CLK_AP_TMR2_RTC_EB] = &ap_tmr2_rtc_eb.common.hw,
1510 [CLK_DCXO_LC_RTC_EB] = &dcxo_lc_rtc_eb.common.hw,
1511 [CLK_BB_CAL_RTC_EB] = &bb_cal_rtc_eb.common.hw,
1512 [CLK_AP_EMMC_RTC_EB] = &ap_emmc_rtc_eb.common.hw,
1513 [CLK_AP_SDIO0_RTC_EB] = &ap_sdio0_rtc_eb.common.hw,
1514 [CLK_AP_SDIO1_RTC_EB] = &ap_sdio1_rtc_eb.common.hw,
1515 [CLK_AP_SDIO2_RTC_EB] = &ap_sdio2_rtc_eb.common.hw,
1516 [CLK_DSI_CSI_TEST_EB] = &dsi_csi_test_eb.common.hw,
1517 [CLK_DJTAG_TCK_EN] = &djtag_tck_en.common.hw,
1518 [CLK_DPHY_REF_EB] = &dphy_ref_eb.common.hw,
1519 [CLK_DMC_REF_EB] = &dmc_ref_eb.common.hw,
1520 [CLK_OTG_REF_EB] = &otg_ref_eb.common.hw,
1521 [CLK_TSEN_EB] = &tsen_eb.common.hw,
1522 [CLK_TMR_EB] = &tmr_eb.common.hw,
1523 [CLK_RC100M_REF_EB] = &rc100m_ref_eb.common.hw,
1524 [CLK_RC100M_FDK_EB] = &rc100m_fdk_eb.common.hw,
1525 [CLK_DEBOUNCE_EB] = &debounce_eb.common.hw,
1526 [CLK_DET_32K_EB] = &det_32k_eb.common.hw,
1527 [CLK_TOP_CSSYS_EB] = &top_cssys_en.common.hw,
1528 [CLK_AP_AXI_EN] = &ap_axi_en.common.hw,
1529 [CLK_SDIO0_2X_EN] = &sdio0_2x_en.common.hw,
1530 [CLK_SDIO0_1X_EN] = &sdio0_1x_en.common.hw,
1531 [CLK_SDIO1_2X_EN] = &sdio1_2x_en.common.hw,
1532 [CLK_SDIO1_1X_EN] = &sdio1_1x_en.common.hw,
1533 [CLK_SDIO2_2X_EN] = &sdio2_2x_en.common.hw,
1534 [CLK_SDIO2_1X_EN] = &sdio2_1x_en.common.hw,
1535 [CLK_EMMC_2X_EN] = &emmc_2x_en.common.hw,
1536 [CLK_EMMC_1X_EN] = &emmc_1x_en.common.hw,
1537 [CLK_PLL_TEST_EN] = &pll_test_en.common.hw,
1538 [CLK_CPHY_CFG_EN] = &cphy_cfg_en.common.hw,
1539 [CLK_DEBUG_TS_EN] = &debug_ts_en.common.hw,
1540 [CLK_ACCESS_AUD_EN] = &access_aud_en.common.hw,
1557 &access_aud_en.common.hw, 0x0, 0x100, BIT(1),
1560 &access_aud_en.common.hw, 0x0, 0x100, BIT(2),
1563 &access_aud_en.common.hw, 0x0, 0x100, BIT(5),
1566 &access_aud_en.common.hw, 0x0, 0x100, BIT(6),
1579 [CLK_AUDCP_WDG_EB] = &audcp_wdg_eb.common.hw,
1580 [CLK_AUDCP_RTC_WDG_EB] = &audcp_rtc_wdg_eb.common.hw,
1581 [CLK_AUDCP_TMR0_EB] = &audcp_tmr0_eb.common.hw,
1582 [CLK_AUDCP_TMR1_EB] = &audcp_tmr1_eb.common.hw,
1599 &access_aud_en.common.hw, 0x0, 0x100, BIT(0),
1602 &access_aud_en.common.hw, 0x0, 0x100, BIT(1),
1605 &access_aud_en.common.hw, 0x0, 0x100, BIT(2),
1608 &access_aud_en.common.hw, 0x0, 0x100, BIT(4),
1611 &access_aud_en.common.hw, 0x0, 0x100, BIT(5),
1614 &access_aud_en.common.hw, 0x0, 0x100, BIT(6),
1617 &access_aud_en.common.hw, 0x0, 0x100, BIT(10),
1620 &access_aud_en.common.hw, 0x0, 0x100, BIT(12),
1623 &access_aud_en.common.hw, 0x0, 0x100, BIT(13),
1626 &access_aud_en.common.hw, 0x0, 0x100, BIT(14),
1629 &access_aud_en.common.hw, 0x0, 0x100, BIT(15),
1632 &access_aud_en.common.hw, 0x0, 0x100, BIT(16),
1635 &access_aud_en.common.hw, 0x0, 0x100, BIT(17),
1638 &access_aud_en.common.hw, 0x0, 0x100, BIT(18),
1641 &access_aud_en.common.hw, 0x0, 0x100, BIT(19),
1644 &access_aud_en.common.hw, 0x0, 0x100, BIT(21),
1647 &access_aud_en.common.hw, 0x0, 0x100, BIT(22),
1650 &access_aud_en.common.hw, 0x0, 0x100, BIT(23),
1677 [CLK_AUDCP_IIS0_EB] = &audcp_iis0_eb.common.hw,
1678 [CLK_AUDCP_IIS1_EB] = &audcp_iis1_eb.common.hw,
1679 [CLK_AUDCP_IIS2_EB] = &audcp_iis2_eb.common.hw,
1680 [CLK_AUDCP_UART_EB] = &audcp_uart_eb.common.hw,
1681 [CLK_AUDCP_DMA_CP_EB] = &audcp_dma_cp_eb.common.hw,
1682 [CLK_AUDCP_DMA_AP_EB] = &audcp_dma_ap_eb.common.hw,
1683 [CLK_AUDCP_SRC48K_EB] = &audcp_src48k_eb.common.hw,
1684 [CLK_AUDCP_MCDT_EB] = &audcp_mcdt_eb.common.hw,
1685 [CLK_AUDCP_VBCIFD_EB] = &audcp_vbcifd_eb.common.hw,
1686 [CLK_AUDCP_VBC_EB] = &audcp_vbc_eb.common.hw,
1687 [CLK_AUDCP_SPLK_EB] = &audcp_splk_eb.common.hw,
1688 [CLK_AUDCP_ICU_EB] = &audcp_icu_eb.common.hw,
1689 [CLK_AUDCP_DMA_AP_ASHB_EB] = &dma_ap_ashb_eb.common.hw,
1690 [CLK_AUDCP_DMA_CP_ASHB_EB] = &dma_cp_ashb_eb.common.hw,
1691 [CLK_AUDCP_AUD_EB] = &audcp_aud_eb.common.hw,
1692 [CLK_AUDCP_VBC_24M_EB] = &audcp_vbc_24m_eb.common.hw,
1693 [CLK_AUDCP_TMR_26M_EB] = &audcp_tmr_26m_eb.common.hw,
1694 [CLK_AUDCP_DVFS_ASHB_EB] = &audcp_dvfs_ashb_eb.common.hw,
1706 static SPRD_GATE_CLK_HW(gpu_core_gate, "gpu-core-gate", &gpu_eb.common.hw,
1711 { .hw = &twpll_384m.hw },
1712 { .hw = &twpll_512m.hw },
1713 { .hw = &lpll_614m4.hw },
1714 { .hw = &twpll_768m.hw },
1715 { .hw = &gpll.common.hw },
1721 static SPRD_GATE_CLK_HW(gpu_mem_gate, "gpu-mem-gate", &gpu_eb.common.hw,
1727 static SPRD_GATE_CLK_HW(gpu_sys_gate, "gpu-sys-gate", &gpu_eb.common.hw,
1730 static SPRD_DIV_CLK_HW(gpu_sys_clk, "gpu-sys-clk", &gpu_eb.common.hw,
1745 [CLK_GPU_CORE_EB] = &gpu_core_gate.common.hw,
1746 [CLK_GPU_CORE] = &gpu_core_clk.common.hw,
1747 [CLK_GPU_MEM_EB] = &gpu_mem_gate.common.hw,
1748 [CLK_GPU_MEM] = &gpu_mem_clk.common.hw,
1749 [CLK_GPU_SYS_EB] = &gpu_sys_gate.common.hw,
1750 [CLK_GPU_SYS] = &gpu_sys_clk.common.hw,
1764 { .hw = &twpll_96m.hw },
1765 { .hw = &twpll_128m.hw },
1766 { .hw = &twpll_153m6.hw },
1772 { .hw = &twpll_76m8.hw },
1773 { .hw = &twpll_128m.hw },
1774 { .hw = &twpll_256m.hw },
1775 { .hw = &twpll_307m2.hw },
1776 { .hw = &twpll_384m.hw },
1777 { .hw = &isppll_468m.hw },
1778 { .hw = &twpll_512m.hw },
1785 { .hw = &twpll_48m.hw },
1786 { .hw = &twpll_76m8.hw },
1787 { .hw = &twpll_96m.hw },
1797 { .hw = &twpll_76m8.hw },
1798 { .hw = &twpll_128m.hw },
1799 { .hw = &twpll_256m.hw },
1800 { .hw = &twpll_384m.hw },
1806 { .hw = &twpll_76m8.hw },
1807 { .hw = &twpll_128m.hw },
1808 { .hw = &twpll_256m.hw },
1809 { .hw = &twpll_384m.hw },
1815 { .hw = &twpll_76m8.hw },
1816 { .hw = &twpll_192m.hw },
1817 { .hw = &twpll_307m2.hw },
1818 { .hw = &twpll_384m.hw },
1824 { .hw = &twpll_192m.hw },
1825 { .hw = &twpll_256m.hw },
1826 { .hw = &twpll_307m2.hw },
1827 { .hw = &twpll_384m.hw },
1828 { .hw = &isppll_468m.hw },
1834 { .hw = &twpll_256m.hw },
1835 { .hw = &twpll_307m2.hw },
1836 { .hw = &twpll_384m.hw },
1837 { .hw = &isppll_468m.hw },
1843 { .hw = &twpll_256m.hw },
1844 { .hw = &twpll_307m2.hw },
1845 { .hw = &twpll_384m.hw },
1846 { .hw = &isppll_468m.hw },
1847 { .hw = &twpll_512m.hw },
1852 static SPRD_GATE_CLK_HW(mipi_csi0, "mipi-csi0", &mm_eb.common.hw,
1855 static SPRD_GATE_CLK_HW(mipi_csi1, "mipi-csi1", &mm_eb.common.hw,
1858 static SPRD_GATE_CLK_HW(mipi_csi2, "mipi-csi2", &mm_eb.common.hw,
1881 [CLK_MM_AHB] = &mm_ahb_clk.common.hw,
1882 [CLK_MM_MTX] = &mm_mtx_clk.common.hw,
1883 [CLK_SENSOR0] = &sensor0_clk.common.hw,
1884 [CLK_SENSOR1] = &sensor1_clk.common.hw,
1885 [CLK_SENSOR2] = &sensor2_clk.common.hw,
1886 [CLK_CPP] = &cpp_clk.common.hw,
1887 [CLK_JPG] = &jpg_clk.common.hw,
1888 [CLK_FD] = &fd_clk.common.hw,
1889 [CLK_DCAM_IF] = &dcam_if_clk.common.hw,
1890 [CLK_DCAM_AXI] = &dcam_axi_clk.common.hw,
1891 [CLK_ISP] = &isp_clk.common.hw,
1892 [CLK_MIPI_CSI0] = &mipi_csi0.common.hw,
1893 [CLK_MIPI_CSI1] = &mipi_csi1.common.hw,
1894 [CLK_MIPI_CSI2] = &mipi_csi2.common.hw,
1906 static SPRD_SC_GATE_CLK_HW(mm_cpp_eb, "mm-cpp-eb", &mm_eb.common.hw,
1908 static SPRD_SC_GATE_CLK_HW(mm_jpg_eb, "mm-jpg-eb", &mm_eb.common.hw,
1910 static SPRD_SC_GATE_CLK_HW(mm_dcam_eb, "mm-dcam-eb", &mm_eb.common.hw,
1912 static SPRD_SC_GATE_CLK_HW(mm_isp_eb, "mm-isp-eb", &mm_eb.common.hw,
1914 static SPRD_SC_GATE_CLK_HW(mm_csi2_eb, "mm-csi2-eb", &mm_eb.common.hw,
1916 static SPRD_SC_GATE_CLK_HW(mm_csi1_eb, "mm-csi1-eb", &mm_eb.common.hw,
1918 static SPRD_SC_GATE_CLK_HW(mm_csi0_eb, "mm-csi0-eb", &mm_eb.common.hw,
1920 static SPRD_SC_GATE_CLK_HW(mm_ckg_eb, "mm-ckg-eb", &mm_eb.common.hw,
1922 static SPRD_SC_GATE_CLK_HW(mm_isp_ahb_eb, "mm-isp-ahb-eb", &mm_eb.common.hw,
1924 static SPRD_SC_GATE_CLK_HW(mm_dvfs_eb, "mm-dvfs-eb", &mm_eb.common.hw,
1926 static SPRD_SC_GATE_CLK_HW(mm_fd_eb, "mm-fd-eb", &mm_eb.common.hw,
1928 static SPRD_SC_GATE_CLK_HW(mm_sensor2_en, "mm-sensor2-en", &mm_eb.common.hw,
1930 static SPRD_SC_GATE_CLK_HW(mm_sensor1_en, "mm-sensor1-en", &mm_eb.common.hw,
1932 static SPRD_SC_GATE_CLK_HW(mm_sensor0_en, "mm-sensor0-en", &mm_eb.common.hw,
1934 static SPRD_SC_GATE_CLK_HW(mm_mipi_csi2_en, "mm-mipi-csi2-en", &mm_eb.common.hw,
1936 static SPRD_SC_GATE_CLK_HW(mm_mipi_csi1_en, "mm-mipi-csi1-en", &mm_eb.common.hw,
1938 static SPRD_SC_GATE_CLK_HW(mm_mipi_csi0_en, "mm-mipi-csi0-en", &mm_eb.common.hw,
1940 static SPRD_SC_GATE_CLK_HW(mm_dcam_axi_en, "mm-dcam-axi-en", &mm_eb.common.hw,
1942 static SPRD_SC_GATE_CLK_HW(mm_isp_axi_en, "mm-isp-axi-en", &mm_eb.common.hw,
1944 static SPRD_SC_GATE_CLK_HW(mm_cphy_en, "mm-cphy-en", &mm_eb.common.hw,
1973 [CLK_MM_CPP_EB] = &mm_cpp_eb.common.hw,
1974 [CLK_MM_JPG_EB] = &mm_jpg_eb.common.hw,
1975 [CLK_MM_DCAM_EB] = &mm_dcam_eb.common.hw,
1976 [CLK_MM_ISP_EB] = &mm_isp_eb.common.hw,
1977 [CLK_MM_CSI2_EB] = &mm_csi2_eb.common.hw,
1978 [CLK_MM_CSI1_EB] = &mm_csi1_eb.common.hw,
1979 [CLK_MM_CSI0_EB] = &mm_csi0_eb.common.hw,
1980 [CLK_MM_CKG_EB] = &mm_ckg_eb.common.hw,
1981 [CLK_ISP_AHB_EB] = &mm_isp_ahb_eb.common.hw,
1982 [CLK_MM_DVFS_EB] = &mm_dvfs_eb.common.hw,
1983 [CLK_MM_FD_EB] = &mm_fd_eb.common.hw,
1984 [CLK_MM_SENSOR2_EB] = &mm_sensor2_en.common.hw,
1985 [CLK_MM_SENSOR1_EB] = &mm_sensor1_en.common.hw,
1986 [CLK_MM_SENSOR0_EB] = &mm_sensor0_en.common.hw,
1987 [CLK_MM_MIPI_CSI2_EB] = &mm_mipi_csi2_en.common.hw,
1988 [CLK_MM_MIPI_CSI1_EB] = &mm_mipi_csi1_en.common.hw,
1989 [CLK_MM_MIPI_CSI0_EB] = &mm_mipi_csi0_en.common.hw,
1990 [CLK_DCAM_AXI_EB] = &mm_dcam_axi_en.common.hw,
1991 [CLK_ISP_AXI_EB] = &mm_isp_axi_en.common.hw,
1992 [CLK_MM_CPHY_EB] = &mm_cphy_en.common.hw,
2101 [CLK_SIM0_EB] = &sim0_eb.common.hw,
2102 [CLK_IIS0_EB] = &iis0_eb.common.hw,
2103 [CLK_IIS1_EB] = &iis1_eb.common.hw,
2104 [CLK_IIS2_EB] = &iis2_eb.common.hw,
2105 [CLK_APB_REG_EB] = &apb_reg_eb.common.hw,
2106 [CLK_SPI0_EB] = &spi0_eb.common.hw,
2107 [CLK_SPI1_EB] = &spi1_eb.common.hw,
2108 [CLK_SPI2_EB] = &spi2_eb.common.hw,
2109 [CLK_SPI3_EB] = &spi3_eb.common.hw,
2110 [CLK_I2C0_EB] = &i2c0_eb.common.hw,
2111 [CLK_I2C1_EB] = &i2c1_eb.common.hw,
2112 [CLK_I2C2_EB] = &i2c2_eb.common.hw,
2113 [CLK_I2C3_EB] = &i2c3_eb.common.hw,
2114 [CLK_I2C4_EB] = &i2c4_eb.common.hw,
2115 [CLK_UART0_EB] = &uart0_eb.common.hw,
2116 [CLK_UART1_EB] = &uart1_eb.common.hw,
2117 [CLK_UART2_EB] = &uart2_eb.common.hw,
2118 [CLK_SIM0_32K_EB] = &sim0_32k_eb.common.hw,
2119 [CLK_SPI0_LFIN_EB] = &spi0_lfin_eb.common.hw,
2120 [CLK_SPI1_LFIN_EB] = &spi1_lfin_eb.common.hw,
2121 [CLK_SPI2_LFIN_EB] = &spi2_lfin_eb.common.hw,
2122 [CLK_SPI3_LFIN_EB] = &spi3_lfin_eb.common.hw,
2123 [CLK_SDIO0_EB] = &sdio0_eb.common.hw,
2124 [CLK_SDIO1_EB] = &sdio1_eb.common.hw,
2125 [CLK_SDIO2_EB] = &sdio2_eb.common.hw,
2126 [CLK_EMMC_EB] = &emmc_eb.common.hw,
2127 [CLK_SDIO0_32K_EB] = &sdio0_32k_eb.common.hw,
2128 [CLK_SDIO1_32K_EB] = &sdio1_32k_eb.common.hw,
2129 [CLK_SDIO2_32K_EB] = &sdio2_32k_eb.common.hw,
2130 [CLK_EMMC_32K_EB] = &emmc_32k_eb.common.hw,