Lines Matching refs:NULL
143 clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0,
145 clk_register_clkdev(clk, NULL, "60000000.clcd");
147 clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
149 clk_register_clkdev(clk, NULL, "94000000.flash");
151 clk = clk_register_fixed_factor(NULL, "sdhci_clk", "ras_ahb_clk", 0, 1,
153 clk_register_clkdev(clk, NULL, "70000000.sdhci");
155 clk = clk_register_fixed_factor(NULL, "gpio1_clk", "ras_apb_clk", 0, 1,
157 clk_register_clkdev(clk, NULL, "a9000000.gpio");
159 clk = clk_register_fixed_factor(NULL, "kbd_clk", "ras_apb_clk", 0, 1,
161 clk_register_clkdev(clk, NULL, "a0000000.kbd");
173 clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1,
175 clk_register_clkdev(clk, "emi", NULL);
177 clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
179 clk_register_clkdev(clk, NULL, "44000000.flash");
181 clk = clk_register_fixed_factor(NULL, "tdm_clk", "ras_ahb_clk", 0, 1,
183 clk_register_clkdev(clk, NULL, "tdm");
185 clk = clk_register_fixed_factor(NULL, "uart1_clk", "ras_apb_clk", 0, 1,
187 clk_register_clkdev(clk, NULL, "b2000000.serial");
189 clk = clk_register_fixed_factor(NULL, "uart2_clk", "ras_apb_clk", 0, 1,
191 clk_register_clkdev(clk, NULL, "b2080000.serial");
193 clk = clk_register_fixed_factor(NULL, "uart3_clk", "ras_apb_clk", 0, 1,
195 clk_register_clkdev(clk, NULL, "b2100000.serial");
197 clk = clk_register_fixed_factor(NULL, "uart4_clk", "ras_apb_clk", 0, 1,
199 clk_register_clkdev(clk, NULL, "b2180000.serial");
201 clk = clk_register_fixed_factor(NULL, "uart5_clk", "ras_apb_clk", 0, 1,
203 clk_register_clkdev(clk, NULL, "b2200000.serial");
251 clk = clk_register_fixed_rate(NULL, "smii_125m_pad_clk", NULL,
253 clk_register_clkdev(clk, "smii_125m_pad", NULL);
255 clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0,
257 clk_register_clkdev(clk, NULL, "90000000.clcd");
259 clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1,
261 clk_register_clkdev(clk, "emi", NULL);
263 clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
265 clk_register_clkdev(clk, NULL, "4c000000.flash");
267 clk = clk_register_fixed_factor(NULL, "i2c1_clk", "ras_ahb_clk", 0, 1,
269 clk_register_clkdev(clk, NULL, "a7000000.i2c");
271 clk = clk_register_fixed_factor(NULL, "pwm_clk", "ras_ahb_clk", 0, 1,
273 clk_register_clkdev(clk, NULL, "a8000000.pwm");
275 clk = clk_register_fixed_factor(NULL, "ssp1_clk", "ras_ahb_clk", 0, 1,
277 clk_register_clkdev(clk, NULL, "a5000000.spi");
279 clk = clk_register_fixed_factor(NULL, "ssp2_clk", "ras_ahb_clk", 0, 1,
281 clk_register_clkdev(clk, NULL, "a6000000.spi");
283 clk = clk_register_fixed_factor(NULL, "can0_clk", "ras_apb_clk", 0, 1,
285 clk_register_clkdev(clk, NULL, "c_can_platform.0");
287 clk = clk_register_fixed_factor(NULL, "can1_clk", "ras_apb_clk", 0, 1,
289 clk_register_clkdev(clk, NULL, "c_can_platform.1");
291 clk = clk_register_fixed_factor(NULL, "i2s_clk", "ras_apb_clk", 0, 1,
293 clk_register_clkdev(clk, NULL, "a9400000.i2s");
295 clk = clk_register_mux(NULL, "i2s_ref_clk", i2s_ref_parents,
300 clk_register_clkdev(clk, "i2s_ref_clk", NULL);
302 clk = clk_register_fixed_factor(NULL, "i2s_sclk", "i2s_ref_clk",
305 clk_register_clkdev(clk, "i2s_sclk", NULL);
307 clk = clk_register_fixed_factor(NULL, "macb1_clk", "ras_apb_clk", 0, 1,
311 clk = clk_register_fixed_factor(NULL, "macb2_clk", "ras_apb_clk", 0, 1,
315 clk = clk_register_mux(NULL, "rs485_clk", uartx_parents,
320 clk_register_clkdev(clk, NULL, "a9300000.serial");
322 clk = clk_register_mux(NULL, "sdhci_clk", sdhci_parents,
327 clk_register_clkdev(clk, NULL, "70000000.sdhci");
329 clk = clk_register_mux(NULL, "smii_pclk", smii0_parents,
333 clk_register_clkdev(clk, NULL, "smii_pclk");
335 clk = clk_register_fixed_factor(NULL, "smii_clk", "smii_pclk", 0, 1, 1);
336 clk_register_clkdev(clk, NULL, "smii");
338 clk = clk_register_mux(NULL, "uart1_clk", uartx_parents,
343 clk_register_clkdev(clk, NULL, "a3000000.serial");
347 clk = clk_register_mux(NULL, "uart2_clk", uartx_parents,
352 clk_register_clkdev(clk, NULL, "a4000000.serial");
356 clk = clk_register_mux(NULL, "uart3_clk", uartx_parents,
361 clk_register_clkdev(clk, NULL, "a9100000.serial");
363 clk = clk_register_mux(NULL, "uart4_clk", uartx_parents,
368 clk_register_clkdev(clk, NULL, "a9200000.serial");
370 clk = clk_register_mux(NULL, "uart5_clk", uartx_parents,
375 clk_register_clkdev(clk, NULL, "60000000.serial");
377 clk = clk_register_mux(NULL, "uart6_clk", uartx_parents,
382 clk_register_clkdev(clk, NULL, "60100000.serial");
392 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000);
393 clk_register_clkdev(clk, "osc_32k_clk", NULL);
395 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, 0, 24000000);
396 clk_register_clkdev(clk, "osc_24m_clk", NULL);
399 clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
401 clk_register_clkdev(clk, NULL, "fc900000.rtc");
404 clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0,
406 clk_register_clkdev(clk, "pll3_clk", NULL);
408 clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_24m_clk", 0, 1,
410 clk_register_clkdev(clk, NULL, "fc880000.wdt");
412 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL,
414 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
415 clk_register_clkdev(clk, "vco1_clk", NULL);
416 clk_register_clkdev(clk1, "pll1_clk", NULL);
418 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL,
420 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
421 clk_register_clkdev(clk, "vco2_clk", NULL);
422 clk_register_clkdev(clk1, "pll2_clk", NULL);
425 clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk",
427 clk_register_clkdev(clk, "cpu_clk", NULL);
429 clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk",
432 clk_register_clkdev(clk, "ahb_clk", NULL);
435 UART_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
437 clk_register_clkdev(clk, "uart_syn_clk", NULL);
438 clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
440 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
445 clk_register_clkdev(clk, "uart0_mclk", NULL);
447 clk = clk_register_gate(NULL, "uart0", "uart0_mclk",
450 clk_register_clkdev(clk, NULL, "d0000000.serial");
453 FIRDA_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
455 clk_register_clkdev(clk, "firda_syn_clk", NULL);
456 clk_register_clkdev(clk1, "firda_syn_gclk", NULL);
458 clk = clk_register_mux(NULL, "firda_mclk", firda_parents,
463 clk_register_clkdev(clk, "firda_mclk", NULL);
465 clk = clk_register_gate(NULL, "firda_clk", "firda_mclk",
468 clk_register_clkdev(clk, NULL, "firda");
473 clk = clk_register_mux(NULL, "gpt0_clk", gpt0_parents,
477 clk_register_clkdev(clk, NULL, "gpt0");
481 clk = clk_register_mux(NULL, "gpt1_mclk", gpt1_parents,
485 clk_register_clkdev(clk, "gpt1_mclk", NULL);
486 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk",
489 clk_register_clkdev(clk, NULL, "gpt1");
493 clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents,
497 clk_register_clkdev(clk, "gpt2_mclk", NULL);
498 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk",
501 clk_register_clkdev(clk, NULL, "gpt2");
505 0, GEN0_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
507 clk_register_clkdev(clk, "gen0_syn_clk", NULL);
508 clk_register_clkdev(clk1, "gen0_syn_gclk", NULL);
511 0, GEN1_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
513 clk_register_clkdev(clk, "gen1_syn_clk", NULL);
514 clk_register_clkdev(clk1, "gen1_syn_gclk", NULL);
516 clk = clk_register_mux(NULL, "gen2_3_par_clk", gen2_3_parents,
520 clk_register_clkdev(clk, "gen2_3_par_clk", NULL);
523 "gen2_3_par_clk", 0, GEN2_CLK_SYNT, NULL, aux_rtbl,
525 clk_register_clkdev(clk, "gen2_syn_clk", NULL);
526 clk_register_clkdev(clk1, "gen2_syn_gclk", NULL);
529 "gen2_3_par_clk", 0, GEN3_CLK_SYNT, NULL, aux_rtbl,
531 clk_register_clkdev(clk, "gen3_syn_clk", NULL);
532 clk_register_clkdev(clk1, "gen3_syn_gclk", NULL);
535 clk = clk_register_gate(NULL, "usbh_clk", "pll3_clk", 0, PERIP1_CLK_ENB,
537 clk_register_clkdev(clk, NULL, "e1800000.ehci");
538 clk_register_clkdev(clk, NULL, "e1900000.ohci");
539 clk_register_clkdev(clk, NULL, "e2100000.ohci");
541 clk = clk_register_fixed_factor(NULL, "usbh.0_clk", "usbh_clk", 0, 1,
543 clk_register_clkdev(clk, "usbh.0_clk", NULL);
545 clk = clk_register_fixed_factor(NULL, "usbh.1_clk", "usbh_clk", 0, 1,
547 clk_register_clkdev(clk, "usbh.1_clk", NULL);
549 clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB,
551 clk_register_clkdev(clk, NULL, "e1100000.usbd");
554 clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2,
556 clk_register_clkdev(clk, "ahbmult2_clk", NULL);
558 clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
561 clk_register_clkdev(clk, "ddr_clk", NULL);
563 clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
566 clk_register_clkdev(clk, "apb_clk", NULL);
568 clk = clk_register_gate(NULL, "amem_clk", "ahb_clk", 0, AMEM_CLK_CFG,
570 clk_register_clkdev(clk, "amem_clk", NULL);
572 clk = clk_register_gate(NULL, "c3_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
574 clk_register_clkdev(clk, NULL, "c3_clk");
576 clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
578 clk_register_clkdev(clk, NULL, "fc400000.dma");
580 clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
582 clk_register_clkdev(clk, NULL, "e0800000.eth");
584 clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
586 clk_register_clkdev(clk, NULL, "d0180000.i2c");
588 clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
590 clk_register_clkdev(clk, NULL, "jpeg");
592 clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
594 clk_register_clkdev(clk, NULL, "fc000000.flash");
597 clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB,
599 clk_register_clkdev(clk, NULL, "d0080000.adc");
601 clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
603 clk_register_clkdev(clk, NULL, "fc980000.gpio");
605 clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
607 clk_register_clkdev(clk, NULL, "d0100000.spi");
610 clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0, RAS_CLK_ENB,
612 clk_register_clkdev(clk, "ras_ahb_clk", NULL);
614 clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0, RAS_CLK_ENB,
616 clk_register_clkdev(clk, "ras_apb_clk", NULL);
619 clk = clk_register_gate(NULL, "ras_32k_clk", "osc_32k_clk", 0,
621 clk_register_clkdev(clk, "ras_32k_clk", NULL);
623 clk = clk_register_gate(NULL, "ras_24m_clk", "osc_24m_clk", 0,
625 clk_register_clkdev(clk, "ras_24m_clk", NULL);
627 clk = clk_register_gate(NULL, "ras_pll1_clk", "pll1_clk", 0,
629 clk_register_clkdev(clk, "ras_pll1_clk", NULL);
631 clk = clk_register_gate(NULL, "ras_pll2_clk", "pll2_clk", 0,
633 clk_register_clkdev(clk, "ras_pll2_clk", NULL);
635 clk = clk_register_gate(NULL, "ras_pll3_clk", "pll3_clk", 0,
637 clk_register_clkdev(clk, "ras_pll3_clk", NULL);
639 clk = clk_register_gate(NULL, "ras_syn0_gclk", "gen0_syn_gclk",
642 clk_register_clkdev(clk, "ras_syn0_gclk", NULL);
644 clk = clk_register_gate(NULL, "ras_syn1_gclk", "gen1_syn_gclk",
647 clk_register_clkdev(clk, "ras_syn1_gclk", NULL);
649 clk = clk_register_gate(NULL, "ras_syn2_gclk", "gen2_syn_gclk",
652 clk_register_clkdev(clk, "ras_syn2_gclk", NULL);
654 clk = clk_register_gate(NULL, "ras_syn3_gclk", "gen3_syn_gclk",
657 clk_register_clkdev(clk, "ras_syn3_gclk", NULL);