Lines Matching refs:CLK_SET_RATE_NO_REPARENT
411 ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
422 ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
433 ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
510 ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
520 ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
530 ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
540 ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
558 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
599 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
612 CLK_SET_RATE_NO_REPARENT, SPEAR1310_GMAC_CLK_CFG,
624 ARRAY_SIZE(gmac_phy_parents), CLK_SET_RATE_NO_REPARENT,
632 CLK_SET_RATE_NO_REPARENT, SPEAR1310_CLCD_CLK_SYNT,
644 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
656 ARRAY_SIZE(i2s_src_parents), CLK_SET_RATE_NO_REPARENT,
668 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
807 CLK_SET_RATE_NO_REPARENT, SPEAR1310_PLL_CFG,
814 CLK_SET_RATE_NO_REPARENT, SPEAR1310_PLL_CFG,
931 CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG1,
939 ARRAY_SIZE(rmii_phy_parents), CLK_SET_RATE_NO_REPARENT,
945 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
956 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
967 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
978 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
989 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
1000 ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
1011 ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
1022 ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
1033 ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
1044 ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
1055 ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
1066 ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
1077 ARRAY_SIZE(ssp1_parents), CLK_SET_RATE_NO_REPARENT,
1088 ARRAY_SIZE(pci_parents), CLK_SET_RATE_NO_REPARENT,
1099 ARRAY_SIZE(tdm_parents), CLK_SET_RATE_NO_REPARENT,
1110 ARRAY_SIZE(tdm_parents), CLK_SET_RATE_NO_REPARENT,