clk/spear/clk-vco-pll.c

66 static unsigned long pll_calc_rate(struct pll_rate_tbl *rtbl,
72 	mode = rtbl[index].mode ? 256 : 1;
73 	rate = (((2 * rate / 10000) * rtbl[index].m) / (mode * rtbl[index].n));
76 		*pll_rate = (rate / (1 << rtbl[index].p)) * 10000;
97 		*prate = pll_calc_rate(pll->vco->rtbl, vco_parent_rate, *index,
145 	struct pll_rate_tbl *rtbl = pll->vco->rtbl;
156 	val |= (rtbl[i].p & PLL_DIV_P_MASK) << PLL_DIV_P_SHIFT;
176 	return pll_calc_rate(vco->rtbl, prate, index, NULL);
231 	struct pll_rate_tbl *rtbl = vco->rtbl;
243 	val |= (rtbl[i].mode & PLL_MODE_MASK) << PLL_MODE_SHIFT;
248 	val |= (rtbl[i].n & PLL_DIV_N_MASK) << PLL_DIV_N_SHIFT;
251 	if (rtbl[i].mode)
252 		val |= (rtbl[i].m & PLL_DITH_FDBK_M_MASK) <<
255 		val |= (rtbl[i].m & PLL_NORM_FDBK_M_MASK) <<
275 		*cfg_reg, struct pll_rate_tbl *rtbl, u8 rtbl_cnt,
286 			!rtbl || !rtbl_cnt) {
302 	vco->rtbl = rtbl;