clk/samsung/clk.c

106 /* register a list of aliases */
108 				const struct samsung_clock_alias *list,
114 	for (idx = 0; idx < nr_clk; idx++, list++) {
115 		if (!list->id) {
121 		clk_hw = ctx->clk_data.hws[list->id];
124 				list->id);
128 		ret = clk_hw_register_clkdev(clk_hw, list->alias,
129 					     list->dev_name);
132 					__func__, list->alias);
136 /* register a list of fixed clocks */
138 		const struct samsung_fixed_rate_clock *list,
144 	for (idx = 0; idx < nr_clk; idx++, list++) {
145 		clk_hw = clk_hw_register_fixed_rate(ctx->dev, list->name,
146 			list->parent_name, list->flags, list->fixed_rate);
149 				list->name);
153 		samsung_clk_add_lookup(ctx, clk_hw, list->id);
159 		ret = clk_hw_register_clkdev(clk_hw, list->name, NULL);
162 				__func__, list->name);
166 /* register a list of fixed factor clocks */
168 		const struct samsung_fixed_factor_clock *list, unsigned int nr_clk)
173 	for (idx = 0; idx < nr_clk; idx++, list++) {
174 		clk_hw = clk_hw_register_fixed_factor(ctx->dev, list->name,
175 			list->parent_name, list->flags, list->mult, list->div);
178 				list->name);
182 		samsung_clk_add_lookup(ctx, clk_hw, list->id);
186 /* register a list of mux clocks */
188 				const struct samsung_mux_clock *list,
194 	for (idx = 0; idx < nr_clk; idx++, list++) {
195 		clk_hw = clk_hw_register_mux(ctx->dev, list->name,
196 			list->parent_names, list->num_parents, list->flags,
197 			ctx->reg_base + list->offset,
198 			list->shift, list->width, list->mux_flags, &ctx->lock);
201 				list->name);
205 		samsung_clk_add_lookup(ctx, clk_hw, list->id);
209 /* register a list of div clocks */
211 				const struct samsung_div_clock *list,
217 	for (idx = 0; idx < nr_clk; idx++, list++) {
218 		if (list->table)
220 				list->name, list->parent_name, list->flags,
221 				ctx->reg_base + list->offset,
222 				list->shift, list->width, list->div_flags,
223 				list->table, &ctx->lock);
225 			clk_hw = clk_hw_register_divider(ctx->dev, list->name,
226 				list->parent_name, list->flags,
227 				ctx->reg_base + list->offset, list->shift,
228 				list->width, list->div_flags, &ctx->lock);
231 				list->name);
235 		samsung_clk_add_lookup(ctx, clk_hw, list->id);
239 /* register a list of gate clocks */
241 				const struct samsung_gate_clock *list,
247 	for (idx = 0; idx < nr_clk; idx++, list++) {
248 		clk_hw = clk_hw_register_gate(ctx->dev, list->name, list->parent_name,
249 				list->flags, ctx->reg_base + list->offset,
250 				list->bit_idx, list->gate_flags, &ctx->lock);
253 				list->name);
257 		samsung_clk_add_lookup(ctx, clk_hw, list->id);
367  * for each CMU. It also add CMU register list to register cache.