clk/samsung/clk-pll.c

658 	u32 con0, con1;
669 	con1 = readl_relaxed(pll->con_reg + 0x4);
671 	if (!(samsung_pll45xx_mp_change(con0, con1, rate))) {
689 	con1 = readl_relaxed(pll->con_reg + 0x4);
690 	con1 &= ~(PLL45XX_AFC_MASK << PLL45XX_AFC_SHIFT);
691 	con1 |= (rate->afc << PLL45XX_AFC_SHIFT);
706 	writel_relaxed(con1, pll->con_reg + 0x4);
795 	u32 con0, con1, lock;
806 	con1 = readl_relaxed(pll->con_reg + 0x4);
808 	if (!(samsung_pll46xx_mpk_change(con0, con1, rate))) {
841 	con1 = readl_relaxed(pll->con_reg + 0x4);
842 	con1 &= ~((PLL46XX_KDIV_MASK << PLL46XX_KDIV_SHIFT) |
845 	con1 |= (rate->kdiv << PLL46XX_KDIV_SHIFT) |
852 	writel_relaxed(con1, pll->con_reg + 0x4);
1128 	u32 con0, con1;
1139 	con1 = readl_relaxed(pll->con_reg + 4);
1154 	con1 &= ~(PLL2650X_K_MASK << PLL2650X_K_SHIFT);
1155 	con1 |= ((rate->kdiv & PLL2650X_K_MASK) << PLL2650X_K_SHIFT);
1156 	writel_relaxed(con1, pll->con_reg + 4);