clk/samsung/clk-pll.c

658 	u32 con0, con1;
668 	con0 = readl_relaxed(pll->con_reg);
671 	if (!(samsung_pll45xx_mp_change(con0, con1, rate))) {
673 		con0 &= ~(PLL45XX_SDIV_MASK << PLL45XX_SDIV_SHIFT);
674 		con0 |= rate->sdiv << PLL45XX_SDIV_SHIFT;
675 		writel_relaxed(con0, pll->con_reg);
681 	con0 &= ~((PLL45XX_MDIV_MASK << PLL45XX_MDIV_SHIFT) |
684 	con0 |= (rate->mdiv << PLL45XX_MDIV_SHIFT) |
707 	writel_relaxed(con0, pll->con_reg);
795 	u32 con0, con1, lock;
805 	con0 = readl_relaxed(pll->con_reg);
808 	if (!(samsung_pll46xx_mpk_change(con0, con1, rate))) {
810 		con0 &= ~(PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
811 		con0 |= rate->sdiv << PLL46XX_SDIV_SHIFT;
812 		writel_relaxed(con0, pll->con_reg);
825 		con0 &= ~((PLL1460X_MDIV_MASK << PLL46XX_MDIV_SHIFT) |
829 		con0 &= ~((PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT) |
833 		con0 |=	rate->vsel << PLL46XX_VSEL_SHIFT;
836 	con0 |= (rate->mdiv << PLL46XX_MDIV_SHIFT) |
851 	writel_relaxed(con0, pll->con_reg);
1128 	u32 con0, con1;
1138 	con0 = readl_relaxed(pll->con_reg);
1145 	con0 &= ~((PLL2650X_M_MASK << PLL2650X_M_SHIFT) |
1148 	con0 |= (rate->mdiv << PLL2650X_M_SHIFT) |
1151 	con0 |= (1 << PLL2650X_PLL_ENABLE_SHIFT);
1152 	writel_relaxed(con0, pll->con_reg);