clk/samsung/clk-exynos5410.c

230 	PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
231 	PLL_36XX_RATE(24 * MHZ, 333000000U, 111, 2, 2, 0),
232 	PLL_36XX_RATE(24 * MHZ, 300000000U, 100, 2, 2, 0),
233 	PLL_36XX_RATE(24 * MHZ, 266000000U, 266, 3, 3, 0),
234 	PLL_36XX_RATE(24 * MHZ, 200000000U, 200, 3, 3, 0),
235 	PLL_36XX_RATE(24 * MHZ, 192000000U, 192, 3, 3, 0),
236 	PLL_36XX_RATE(24 * MHZ, 166000000U, 166, 3, 3, 0),
237 	PLL_36XX_RATE(24 * MHZ, 133000000U, 266, 3, 4, 0),
238 	PLL_36XX_RATE(24 * MHZ, 100000000U, 200, 3, 4, 0),
239 	PLL_36XX_RATE(24 * MHZ, 66000000U,  176, 2, 5, 0),
274 	if (!IS_ERR(xxti) && clk_get_rate(xxti) == 24 * MHZ)