Lines Matching refs:list
408 struct rockchip_pll_clock *list,
414 for (idx = 0; idx < nr_pll; idx++, list++) {
415 clk = rockchip_clk_register_pll(ctx, list->type, list->name,
416 list->parent_names, list->num_parents,
417 list->con_offset, grf_lock_offset,
418 list->lock_shift, list->mode_offset,
419 list->mode_shift, list->rate_table,
420 list->flags, list->pll_flags);
423 list->name);
427 rockchip_clk_add_lookup(ctx, clk, list->id);
432 unsigned long rockchip_clk_find_max_clk_id(struct rockchip_clk_branch *list,
438 for (idx = 0; idx < nr_clk; idx++, list++) {
439 if (list->id > max)
440 max = list->id;
441 if (list->child && list->child->id > max)
442 max = list->id;
450 struct rockchip_clk_branch *list,
457 for (idx = 0; idx < nr_clk; idx++, list++) {
458 flags = list->flags;
461 switch (list->branch_type) {
463 if (list->mux_table)
464 clk = clk_register_mux_table(NULL, list->name,
465 list->parent_names, list->num_parents,
467 ctx->reg_base + list->muxdiv_offset,
468 list->mux_shift, list->mux_width,
469 list->mux_flags, list->mux_table,
472 clk = clk_register_mux(NULL, list->name,
473 list->parent_names, list->num_parents,
475 ctx->reg_base + list->muxdiv_offset,
476 list->mux_shift, list->mux_width,
477 list->mux_flags, &ctx->lock);
480 clk = rockchip_clk_register_muxgrf(list->name,
481 list->parent_names, list->num_parents,
482 flags, ctx->grf, list->muxdiv_offset,
483 list->mux_shift, list->mux_width,
484 list->mux_flags);
487 if (list->div_table)
489 list->name, list->parent_names[0],
491 ctx->reg_base + list->muxdiv_offset,
492 list->div_shift, list->div_width,
493 list->div_flags, list->div_table,
496 clk = clk_register_divider(NULL, list->name,
497 list->parent_names[0], flags,
498 ctx->reg_base + list->muxdiv_offset,
499 list->div_shift, list->div_width,
500 list->div_flags, &ctx->lock);
503 clk = rockchip_clk_register_frac_branch(ctx, list->name,
504 list->parent_names, list->num_parents,
505 ctx->reg_base, list->muxdiv_offset,
506 list->div_flags,
507 list->gate_offset, list->gate_shift,
508 list->gate_flags, flags, list->child,
512 clk = rockchip_clk_register_halfdiv(list->name,
513 list->parent_names, list->num_parents,
514 ctx->reg_base, list->muxdiv_offset,
515 list->mux_shift, list->mux_width,
516 list->mux_flags, list->div_shift,
517 list->div_width, list->div_flags,
518 list->gate_offset, list->gate_shift,
519 list->gate_flags, flags, &ctx->lock);
524 clk = clk_register_gate(NULL, list->name,
525 list->parent_names[0], flags,
526 ctx->reg_base + list->gate_offset,
527 list->gate_shift, list->gate_flags, &ctx->lock);
530 clk = rockchip_clk_register_branch(list->name,
531 list->parent_names, list->num_parents,
532 ctx->reg_base, list->muxdiv_offset,
533 list->mux_shift,
534 list->mux_width, list->mux_flags,
535 list->mux_table, list->div_offset,
536 list->div_shift, list->div_width,
537 list->div_flags, list->div_table,
538 list->gate_offset, list->gate_shift,
539 list->gate_flags, flags, &ctx->lock);
543 list->name,
544 list->parent_names, list->num_parents,
545 ctx->reg_base + list->muxdiv_offset,
546 list->div_shift
551 list->name, list->parent_names,
552 list->num_parents,
553 ctx->reg_base + list->muxdiv_offset,
554 list->div_shift, list->div_flags, &ctx->lock);
558 list->name, list->parent_names,
559 list->num_parents, ctx->reg_base,
560 list->div_shift, list->div_width,
561 list->gate_offset, list->gate_shift,
562 list->gate_flags, flags, &ctx->lock);
566 list->name, list->flags,
567 list->parent_names, list->num_parents,
568 list->muxdiv_offset, list->mux_shift,
569 list->mux_width, list->div_shift,
570 list->div_width, list->div_flags,
578 __func__, list->branch_type);
584 __func__, list->name, PTR_ERR(clk));
588 rockchip_clk_add_lookup(ctx, clk, list->id);