Lines Matching refs:CLK_PLL1
33 CLK_PLL1,
49 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
52 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
56 DEF_BASE("lb", R8A7790_CLK_LB, CLK_TYPE_GEN2_LB, CLK_PLL1),
57 DEF_BASE("adsp", R8A7790_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
58 DEF_BASE("sdh", R8A7790_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
59 DEF_BASE("sd0", R8A7790_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
60 DEF_BASE("sd1", R8A7790_CLK_SD1, CLK_TYPE_GEN2_SD1, CLK_PLL1),
64 DEF_FIXED("z2", R8A7790_CLK_Z2, CLK_PLL1, 2, 1),
65 DEF_FIXED("zg", R8A7790_CLK_ZG, CLK_PLL1, 3, 1),
66 DEF_FIXED("zx", R8A7790_CLK_ZX, CLK_PLL1, 3, 1),
67 DEF_FIXED("zs", R8A7790_CLK_ZS, CLK_PLL1, 6, 1),
68 DEF_FIXED("hp", R8A7790_CLK_HP, CLK_PLL1, 12, 1),
69 DEF_FIXED("i", R8A7790_CLK_I, CLK_PLL1, 2, 1),
70 DEF_FIXED("b", R8A7790_CLK_B, CLK_PLL1, 12, 1),
71 DEF_FIXED("p", R8A7790_CLK_P, CLK_PLL1, 24, 1),
72 DEF_FIXED("cl", R8A7790_CLK_CL, CLK_PLL1, 48, 1),
73 DEF_FIXED("m2", R8A7790_CLK_M2, CLK_PLL1, 8, 1),
74 DEF_FIXED("imp", R8A7790_CLK_IMP, CLK_PLL1, 4, 1),
80 DEF_FIXED("r", R8A7790_CLK_R, CLK_PLL1, 49152, 1),
81 DEF_FIXED("osc", R8A7790_CLK_OSC, CLK_PLL1, 12288, 1),