clk/qcom/gdsc.c

60 static int gdsc_check_status(struct gdsc *sc, enum gdsc_status status)
66 	if (sc->flags & POLL_CFG_GDSCR)
67 		reg = sc->gdscr + CFG_GDSCR_OFFSET;
68 	else if (sc->gds_hw_ctrl)
69 		reg = sc->gds_hw_ctrl;
71 		reg = sc->gdscr;
73 	ret = regmap_read(sc->regmap, reg, &val);
77 	if (sc->flags & POLL_CFG_GDSCR) {
96 static int gdsc_hwctrl(struct gdsc *sc, bool en)
100 	return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val);
103 static int gdsc_poll_status(struct gdsc *sc, enum gdsc_status status)
109 		if (gdsc_check_status(sc, status))
113 	if (gdsc_check_status(sc, status))
119 static int gdsc_update_collapse_bit(struct gdsc *sc, bool val)
124 	if (sc->collapse_mask) {
125 		reg = sc->collapse_ctrl;
126 		mask = sc->collapse_mask;
128 		reg = sc->gdscr;
132 	ret = regmap_update_bits(sc->regmap, reg, mask, val ? mask : 0);
139 static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status,
144 	if (status == GDSC_ON && sc->rsupply) {
145 		ret = regulator_enable(sc->rsupply);
150 	ret = gdsc_update_collapse_bit(sc, status == GDSC_OFF);
153 	if ((sc->flags & VOTABLE) && status == GDSC_OFF && !wait) {
163 	if (sc->gds_hw_ctrl) {
177 	ret = gdsc_poll_status(sc, status);
178 	WARN(ret, "%s status stuck at 'o%s'", sc->pd.name, status ? "ff" : "n");
180 	if (!ret && status == GDSC_OFF && sc->rsupply) {
181 		ret = regulator_disable(sc->rsupply);
189 static inline int gdsc_deassert_reset(struct gdsc *sc)
193 	for (i = 0; i < sc->reset_count; i++)
194 		sc->rcdev->ops->deassert(sc->rcdev, sc->resets[i]);
198 static inline int gdsc_assert_reset(struct gdsc *sc)
202 	for (i = 0; i < sc->reset_count; i++)
203 		sc->rcdev->ops->assert(sc->rcdev, sc->resets[i]);
207 static inline void gdsc_force_mem_on(struct gdsc *sc)
212 	if (!(sc->flags & NO_RET_PERIPH))
215 	for (i = 0; i < sc->cxc_count; i++)
216 		regmap_update_bits(sc->regmap, sc->cxcs[i], mask, mask);
219 static inline void gdsc_clear_mem_on(struct gdsc *sc)
224 	if (!(sc->flags & NO_RET_PERIPH))
227 	for (i = 0; i < sc->cxc_count; i++)
228 		regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0);
231 static inline void gdsc_deassert_clamp_io(struct gdsc *sc)
233 	regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
237 static inline void gdsc_assert_clamp_io(struct gdsc *sc)
239 	regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
243 static inline void gdsc_assert_reset_aon(struct gdsc *sc)
245 	regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
248 	regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
252 static void gdsc_retain_ff_on(struct gdsc *sc)
256 	regmap_update_bits(sc->regmap, sc->gdscr, mask, mask);
261 	struct gdsc *sc = domain_to_gdsc(domain);
264 	if (sc->pwrsts == PWRSTS_ON)
265 		return gdsc_deassert_reset(sc);
267 	if (sc->flags & SW_RESET) {
268 		gdsc_assert_reset(sc);
270 		gdsc_deassert_reset(sc);
273 	if (sc->flags & CLAMP_IO) {
274 		if (sc->flags & AON_RESET)
275 			gdsc_assert_reset_aon(sc);
276 		gdsc_deassert_clamp_io(sc);
279 	ret = gdsc_toggle_logic(sc, GDSC_ON, false);
283 	if (sc->pwrsts & PWRSTS_OFF)
284 		gdsc_force_mem_on(sc);
296 	if (sc->flags & HW_CTRL) {
297 		ret = gdsc_hwctrl(sc, true);
311 	if (sc->flags & RETAIN_FF_ENABLE)
312 		gdsc_retain_ff_on(sc);
319 	struct gdsc *sc = domain_to_gdsc(domain);
322 	if (sc->pwrsts == PWRSTS_ON)
323 		return gdsc_assert_reset(sc);
326 	if (sc->flags & HW_CTRL) {
327 		ret = gdsc_hwctrl(sc, false);
338 		ret = gdsc_poll_status(sc, GDSC_ON);
343 	if (sc->pwrsts & PWRSTS_OFF)
344 		gdsc_clear_mem_on(sc);
353 	if (sc->pwrsts == PWRSTS_RET_ON)
356 	ret = gdsc_toggle_logic(sc, GDSC_OFF, domain->synced_poweroff);
360 	if (sc->flags & CLAMP_IO)
361 		gdsc_assert_clamp_io(sc);
366 static int gdsc_init(struct gdsc *sc)
379 	if (!sc->en_rest_wait_val)
380 		sc->en_rest_wait_val = EN_REST_WAIT_VAL;
381 	if (!sc->en_few_wait_val)
382 		sc->en_few_wait_val = EN_FEW_WAIT_VAL;
383 	if (!sc->clk_dis_wait_val)
384 		sc->clk_dis_wait_val = CLK_DIS_WAIT_VAL;
386 	val = sc->en_rest_wait_val << EN_REST_WAIT_SHIFT |
387 		sc->en_few_wait_val << EN_FEW_WAIT_SHIFT |
388 		sc->clk_dis_wait_val << CLK_DIS_WAIT_SHIFT;
390 	ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val);
395 	if (sc->pwrsts == PWRSTS_ON) {
396 		ret = gdsc_toggle_logic(sc, GDSC_ON, false);
401 	on = gdsc_check_status(sc, GDSC_ON);
407 		if (sc->rsupply) {
408 			ret = regulator_enable(sc->rsupply);
417 		if (sc->flags & VOTABLE) {
418 			ret = gdsc_update_collapse_bit(sc, false);
424 		if (sc->flags & HW_CTRL) {
425 			ret = gdsc_hwctrl(sc, true);
435 		if (sc->flags & RETAIN_FF_ENABLE)
436 			gdsc_retain_ff_on(sc);
437 	} else if (sc->flags & ALWAYS_ON) {
439 		gdsc_enable(&sc->pd);
443 	if (on || (sc->pwrsts & PWRSTS_RET))
444 		gdsc_force_mem_on(sc);
446 		gdsc_clear_mem_on(sc);
448 	if (sc->flags & ALWAYS_ON)
449 		sc->pd.flags |= GENPD_FLAG_ALWAYS_ON;
450 	if (!sc->pd.power_off)
451 		sc->pd.power_off = gdsc_disable;
452 	if (!sc->pd.power_on)
453 		sc->pd.power_on = gdsc_enable;
455 	ret = pm_genpd_init(&sc->pd, NULL, !on);
462 	if (on && sc->rsupply)
463 		regulator_disable(sc->rsupply);
565 	struct gdsc *sc = domain_to_gdsc(domain);
569 	if (sc->rsupply)
570 		ret = regulator_enable(sc->rsupply);