Lines Matching refs:pll
14 * struct clk_pll - mxs pll clock
15 * @hw: clk_hw for the pll
16 * @base: base address of the pll
18 * @rate: the clock rate of the pll
20 * The mxs pll is a fixed rate clock with power and gate control,
34 struct clk_pll *pll = to_clk_pll(hw);
36 writel_relaxed(1 << pll->power, pll->base + SET);
45 struct clk_pll *pll = to_clk_pll(hw);
47 writel_relaxed(1 << pll->power, pll->base + CLR);
52 struct clk_pll *pll = to_clk_pll(hw);
54 writel_relaxed(1 << 31, pll->base + CLR);
61 struct clk_pll *pll = to_clk_pll(hw);
63 writel_relaxed(1 << 31, pll->base + SET);
69 struct clk_pll *pll = to_clk_pll(hw);
71 return pll->rate;
85 struct clk_pll *pll;
89 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
90 if (!pll)
99 pll->base = base;
100 pll->rate = rate;
101 pll->power = power;
102 pll->hw.init = &init;
104 clk = clk_register(NULL, &pll->hw);
106 kfree(pll);