clk/mvebu/clk-corediv.c

81 	struct clk_corediv *corediv = to_corediv_clk(hwclk);
82 	const struct clk_corediv_soc_desc *soc_desc = corediv->soc_desc;
83 	const struct clk_corediv_desc *desc = corediv->desc;
86 	return !!(readl(corediv->reg) & enable_mask);
91 	struct clk_corediv *corediv = to_corediv_clk(hwclk);
92 	const struct clk_corediv_soc_desc *soc_desc = corediv->soc_desc;
93 	const struct clk_corediv_desc *desc = corediv->desc;
97 	spin_lock_irqsave(&corediv->lock, flags);
99 	reg = readl(corediv->reg);
101 	writel(reg, corediv->reg);
103 	spin_unlock_irqrestore(&corediv->lock, flags);
110 	struct clk_corediv *corediv = to_corediv_clk(hwclk);
111 	const struct clk_corediv_soc_desc *soc_desc = corediv->soc_desc;
112 	const struct clk_corediv_desc *desc = corediv->desc;
116 	spin_lock_irqsave(&corediv->lock, flags);
118 	reg = readl(corediv->reg);
120 	writel(reg, corediv->reg);
122 	spin_unlock_irqrestore(&corediv->lock, flags);
128 	struct clk_corediv *corediv = to_corediv_clk(hwclk);
129 	const struct clk_corediv_soc_desc *soc_desc = corediv->soc_desc;
130 	const struct clk_corediv_desc *desc = corediv->desc;
133 	reg = readl(corediv->reg + soc_desc->ratio_offset);
156 	struct clk_corediv *corediv = to_corediv_clk(hwclk);
157 	const struct clk_corediv_soc_desc *soc_desc = corediv->soc_desc;
158 	const struct clk_corediv_desc *desc = corediv->desc;
164 	spin_lock_irqsave(&corediv->lock, flags);
167 	reg = readl(corediv->reg + soc_desc->ratio_offset);
170 	writel(reg, corediv->reg + soc_desc->ratio_offset);
173 	reg = readl(corediv->reg) | BIT(desc->fieldbit);
174 	writel(reg, corediv->reg);
177 	reg = readl(corediv->reg) | soc_desc->ratio_reload;
178 	writel(reg, corediv->reg);
186 	writel(reg, corediv->reg);
189 	spin_unlock_irqrestore(&corediv->lock, flags);
255 	struct clk_corediv *corediv;
275 	/* corediv holds the clock specific array */
276 	corediv = kcalloc(clk_data.clk_num, sizeof(struct clk_corediv),
278 	if (WARN_ON(!corediv))
281 	spin_lock_init(&corediv->lock);
292 		corediv[i].soc_desc = soc_desc;
293 		corediv[i].desc = soc_desc->descs + i;
294 		corediv[i].reg = base;
295 		corediv[i].hw.init = &init;
297 		clks[i] = clk_register(NULL, &corediv[i].hw);
315 CLK_OF_DECLARE(armada370_corediv_clk, "marvell,armada-370-corediv-clock",
322 CLK_OF_DECLARE(armada375_corediv_clk, "marvell,armada-375-corediv-clock",
329 CLK_OF_DECLARE(armada380_corediv_clk, "marvell,armada-380-corediv-clock",
336 CLK_OF_DECLARE(mv98dx3236_corediv_clk, "marvell,mv98dx3236-corediv-clock",