clk/mmp/clk-audio.c

119 	struct mmp2_audio_clk *priv = container_of(hw, struct mmp2_audio_clk, audio_pll_hw);
125 	aud_pll_ctrl0 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL0);
133 	aud_pll_ctrl1 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL1);
197 	struct mmp2_audio_clk *priv = container_of(hw, struct mmp2_audio_clk, audio_pll_hw);
216 			writel(val, priv->mmio_base + SSPA_AUD_PLL_CTRL0);
220 			writel(val, priv->mmio_base + SSPA_AUD_PLL_CTRL1);
235 static int register_clocks(struct mmp2_audio_clk *priv, struct device *dev)
238 		{ .hw = &priv->audio_pll_hw },
242 		{ .hw = &priv->audio_pll_hw },
247 	priv->audio_pll_hw.init = CLK_HW_INIT_FW_NAME("audio_pll",
250 	ret = devm_clk_hw_register(dev, &priv->audio_pll_hw);
254 	priv->sspa_mux.hw.init = CLK_HW_INIT_PARENTS_DATA("sspa_mux",
257 	priv->sspa_mux.reg = priv->mmio_base + SSPA_AUD_CTRL;
258 	priv->sspa_mux.mask = 1;
259 	priv->sspa_mux.shift = SSPA_AUD_CTRL_SSPA0_MUX_SHIFT;
260 	ret = devm_clk_hw_register(dev, &priv->sspa_mux.hw);
264 	priv->sysclk_div.hw.init = CLK_HW_INIT_HW("sys_div",
265 				&priv->sspa_mux.hw, &clk_divider_ops,
267 	priv->sysclk_div.reg = priv->mmio_base + SSPA_AUD_CTRL;
268 	priv->sysclk_div.shift = SSPA_AUD_CTRL_SYSCLK_DIV_SHIFT;
269 	priv->sysclk_div.width = 6;
270 	priv->sysclk_div.flags = CLK_DIVIDER_ONE_BASED;
271 	priv->sysclk_div.flags |= CLK_DIVIDER_ROUND_CLOSEST;
272 	priv->sysclk_div.flags |= CLK_DIVIDER_ALLOW_ZERO;
273 	ret = devm_clk_hw_register(dev, &priv->sysclk_div.hw);
277 	priv->sysclk_gate.hw.init = CLK_HW_INIT_HW("sys_clk",
278 				&priv->sysclk_div.hw, &clk_gate_ops,
280 	priv->sysclk_gate.reg = priv->mmio_base + SSPA_AUD_CTRL;
281 	priv->sysclk_gate.bit_idx = SSPA_AUD_CTRL_SYSCLK_SHIFT;
282 	ret = devm_clk_hw_register(dev, &priv->sysclk_gate.hw);
286 	priv->sspa0_div.hw.init = CLK_HW_INIT_HW("sspa0_div",
287 				&priv->sspa_mux.hw, &clk_divider_ops, 0);
288 	priv->sspa0_div.reg = priv->mmio_base + SSPA_AUD_CTRL;
289 	priv->sspa0_div.shift = SSPA_AUD_CTRL_SSPA0_DIV_SHIFT;
290 	priv->sspa0_div.width = 6;
291 	priv->sspa0_div.flags = CLK_DIVIDER_ONE_BASED;
292 	priv->sspa0_div.flags |= CLK_DIVIDER_ROUND_CLOSEST;
293 	priv->sspa0_div.flags |= CLK_DIVIDER_ALLOW_ZERO;
294 	ret = devm_clk_hw_register(dev, &priv->sspa0_div.hw);
298 	priv->sspa0_gate.hw.init = CLK_HW_INIT_HW("sspa0_clk",
299 				&priv->sspa0_div.hw, &clk_gate_ops,
301 	priv->sspa0_gate.reg = priv->mmio_base + SSPA_AUD_CTRL;
302 	priv->sspa0_gate.bit_idx = SSPA_AUD_CTRL_SSPA0_SHIFT;
303 	ret = devm_clk_hw_register(dev, &priv->sspa0_gate.hw);
307 	priv->sspa1_mux.hw.init = CLK_HW_INIT_PARENTS_DATA("sspa1_mux",
310 	priv->sspa1_mux.reg = priv->mmio_base + SSPA_AUD_CTRL;
311 	priv->sspa1_mux.mask = 1;
312 	priv->sspa1_mux.shift = SSPA_AUD_CTRL_SSPA1_MUX_SHIFT;
313 	ret = devm_clk_hw_register(dev, &priv->sspa1_mux.hw);
317 	priv->sspa1_div.hw.init = CLK_HW_INIT_HW("sspa1_div",
318 				&priv->sspa1_mux.hw, &clk_divider_ops, 0);
319 	priv->sspa1_div.reg = priv->mmio_base + SSPA_AUD_CTRL;
320 	priv->sspa1_div.shift = SSPA_AUD_CTRL_SSPA1_DIV_SHIFT;
321 	priv->sspa1_div.width = 6;
322 	priv->sspa1_div.flags = CLK_DIVIDER_ONE_BASED;
323 	priv->sspa1_div.flags |= CLK_DIVIDER_ROUND_CLOSEST;
324 	priv->sspa1_div.flags |= CLK_DIVIDER_ALLOW_ZERO;
325 	ret = devm_clk_hw_register(dev, &priv->sspa1_div.hw);
329 	priv->sspa1_gate.hw.init = CLK_HW_INIT_HW("sspa1_clk",
330 				&priv->sspa1_div.hw, &clk_gate_ops,
332 	priv->sspa1_gate.reg = priv->mmio_base + SSPA_AUD_CTRL;
333 	priv->sspa1_gate.bit_idx = SSPA_AUD_CTRL_SSPA1_SHIFT;
334 	ret = devm_clk_hw_register(dev, &priv->sspa1_gate.hw);
338 	priv->clk_data.hws[MMP2_CLK_AUDIO_SYSCLK] = &priv->sysclk_gate.hw;
339 	priv->clk_data.hws[MMP2_CLK_AUDIO_SSPA0] = &priv->sspa0_gate.hw;
340 	priv->clk_data.hws[MMP2_CLK_AUDIO_SSPA1] = &priv->sspa1_gate.hw;
341 	priv->clk_data.num = CLK_AUDIO_NR_CLKS;
344 				      &priv->clk_data);
349 	struct mmp2_audio_clk *priv;
352 	priv = devm_kzalloc(&pdev->dev,
353 			    struct_size(priv, clk_data.hws,
356 	if (!priv)
359 	spin_lock_init(&priv->lock);
360 	platform_set_drvdata(pdev, priv);
362 	priv->mmio_base = devm_platform_ioremap_resource(pdev, 0);
363 	if (IS_ERR(priv->mmio_base))
364 		return PTR_ERR(priv->mmio_base);
375 	ret = register_clocks(priv, &pdev->dev);
398 	struct mmp2_audio_clk *priv = dev_get_drvdata(dev);
400 	priv->aud_ctrl = readl(priv->mmio_base + SSPA_AUD_CTRL);
401 	priv->aud_pll_ctrl0 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL0);
402 	priv->aud_pll_ctrl1 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL1);
410 	struct mmp2_audio_clk *priv = dev_get_drvdata(dev);
413 	writel(priv->aud_ctrl, priv->mmio_base + SSPA_AUD_CTRL);
414 	writel(priv->aud_pll_ctrl0, priv->mmio_base + SSPA_AUD_PLL_CTRL0);
415 	writel(priv->aud_pll_ctrl1, priv->mmio_base + SSPA_AUD_PLL_CTRL1);