Lines Matching refs:hw
121 .hw.init = &(struct clk_init_data){
138 .hw.init = &(struct clk_init_data){
142 &gxbb_fixed_pll_dco.hw
155 .hw.init = &(struct clk_init_data){
198 .hw.init = &(struct clk_init_data){
202 &gxbb_hdmi_pll_pre_mult.hw
252 .hw.init = &(struct clk_init_data){
274 .hw.init = &(struct clk_init_data){
278 &gxbb_hdmi_pll_dco.hw
292 .hw.init = &(struct clk_init_data){
296 &gxbb_hdmi_pll_od.hw
310 .hw.init = &(struct clk_init_data){
314 &gxbb_hdmi_pll_od2.hw
328 .hw.init = &(struct clk_init_data){
332 &gxl_hdmi_pll_dco.hw
346 .hw.init = &(struct clk_init_data){
350 &gxl_hdmi_pll_od.hw
364 .hw.init = &(struct clk_init_data){
368 &gxl_hdmi_pll_od2.hw
403 .hw.init = &(struct clk_init_data){
420 .hw.init = &(struct clk_init_data){
424 &gxbb_sys_pll_dco.hw
468 .hw.init = &(struct clk_init_data){
522 .hw.init = &(struct clk_init_data){
539 .hw.init = &(struct clk_init_data){
561 .hw.init = &(struct clk_init_data){
565 &gxbb_fixed_pll.hw
576 .hw.init = &(struct clk_init_data){
580 &gxbb_fclk_div2_div.hw
590 .hw.init = &(struct clk_init_data){
593 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
603 .hw.init = &(struct clk_init_data){
607 &gxbb_fclk_div3_div.hw
628 .hw.init = &(struct clk_init_data){
631 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
641 .hw.init = &(struct clk_init_data){
645 &gxbb_fclk_div4_div.hw
654 .hw.init = &(struct clk_init_data){
657 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
667 .hw.init = &(struct clk_init_data){
671 &gxbb_fclk_div5_div.hw
680 .hw.init = &(struct clk_init_data){
683 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
693 .hw.init = &(struct clk_init_data){
697 &gxbb_fclk_div7_div.hw
709 .hw.init = &(struct clk_init_data){
712 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
736 .hw.init = &(struct clk_init_data){
740 &gxbb_mpll_prediv.hw
765 .hw.init = &(struct clk_init_data){
769 &gxbb_mpll_prediv.hw
780 .hw.init = &(struct clk_init_data){
817 .hw.init = &(struct clk_init_data){
821 &gxbb_mpll_prediv.hw
832 .hw.init = &(struct clk_init_data){
835 .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll1_div.hw },
860 .hw.init = &(struct clk_init_data){
864 &gxbb_mpll_prediv.hw
875 .hw.init = &(struct clk_init_data){
878 .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll2_div.hw },
887 { .hw = &gxbb_fclk_div7.hw },
888 { .hw = &gxbb_mpll1.hw },
889 { .hw = &gxbb_mpll2.hw },
890 { .hw = &gxbb_fclk_div4.hw },
891 { .hw = &gxbb_fclk_div3.hw },
892 { .hw = &gxbb_fclk_div5.hw },
902 .hw.init = &(struct clk_init_data){
921 .hw.init = &(struct clk_init_data){
925 &gxbb_mpeg_clk_sel.hw
937 .hw.init = &(struct clk_init_data){
941 &gxbb_mpeg_clk_div.hw
954 .hw.init = &(struct clk_init_data){
960 { .hw = &gxbb_clk81.hw },
972 .hw.init = &(struct clk_init_data){
976 &gxbb_sar_adc_clk_sel.hw
988 .hw.init = &(struct clk_init_data){
992 &gxbb_sar_adc_clk_div.hw
1008 { .hw = &gxbb_gp0_pll.hw },
1009 { .hw = &gxbb_mpll2.hw },
1010 { .hw = &gxbb_mpll1.hw },
1011 { .hw = &gxbb_fclk_div7.hw },
1012 { .hw = &gxbb_fclk_div4.hw },
1013 { .hw = &gxbb_fclk_div3.hw },
1014 { .hw = &gxbb_fclk_div5.hw },
1023 .hw.init = &(struct clk_init_data){
1044 .hw.init = &(struct clk_init_data){
1048 &gxbb_mali_0_sel.hw
1060 .hw.init = &(struct clk_init_data){
1064 &gxbb_mali_0_div.hw
1077 .hw.init = &(struct clk_init_data){
1098 .hw.init = &(struct clk_init_data){
1102 &gxbb_mali_1_sel.hw
1114 .hw.init = &(struct clk_init_data){
1118 &gxbb_mali_1_div.hw
1126 &gxbb_mali_0.hw,
1127 &gxbb_mali_1.hw,
1136 .hw.init = &(struct clk_init_data){
1153 .hw.init = &(struct clk_init_data){
1157 &gxbb_mpll0.hw,
1158 &gxbb_mpll1.hw,
1159 &gxbb_mpll2.hw,
1172 .hw.init = &(struct clk_init_data){
1176 &gxbb_cts_amclk_sel.hw
1188 .hw.init = &(struct clk_init_data){
1192 &gxbb_cts_amclk_div.hw
1207 .hw.init = &(struct clk_init_data) {
1211 &gxbb_mpll0.hw,
1212 &gxbb_mpll1.hw,
1213 &gxbb_mpll2.hw,
1226 .hw.init = &(struct clk_init_data) {
1230 &gxbb_cts_mclk_i958_sel.hw
1242 .hw.init = &(struct clk_init_data){
1246 &gxbb_cts_mclk_i958_div.hw
1259 .hw.init = &(struct clk_init_data){
1263 &gxbb_cts_amclk.hw,
1264 &gxbb_cts_mclk_i958.hw
1283 { .hw = &gxbb_fclk_div3.hw },
1284 { .hw = &gxbb_fclk_div5.hw },
1293 .hw.init = &(struct clk_init_data){
1308 .hw.init = &(struct clk_init_data){
1312 &gxbb_32k_clk_sel.hw
1324 .hw.init = &(struct clk_init_data){
1328 &gxbb_32k_clk_div.hw
1337 { .hw = &gxbb_fclk_div2.hw },
1338 { .hw = &gxbb_fclk_div3.hw },
1339 { .hw = &gxbb_fclk_div5.hw },
1340 { .hw = &gxbb_fclk_div7.hw },
1356 .hw.init = &(struct clk_init_data) {
1372 .hw.init = &(struct clk_init_data) {
1376 &gxbb_sd_emmc_a_clk0_sel.hw
1388 .hw.init = &(struct clk_init_data){
1392 &gxbb_sd_emmc_a_clk0_div.hw
1406 .hw.init = &(struct clk_init_data) {
1422 .hw.init = &(struct clk_init_data) {
1426 &gxbb_sd_emmc_b_clk0_sel.hw
1438 .hw.init = &(struct clk_init_data){
1442 &gxbb_sd_emmc_b_clk0_div.hw
1456 .hw.init = &(struct clk_init_data) {
1472 .hw.init = &(struct clk_init_data) {
1476 &gxbb_sd_emmc_c_clk0_sel.hw
1488 .hw.init = &(struct clk_init_data){
1492 &gxbb_sd_emmc_c_clk0_div.hw
1502 &gxbb_fclk_div4.hw,
1503 &gxbb_fclk_div3.hw,
1504 &gxbb_fclk_div5.hw,
1505 &gxbb_fclk_div7.hw,
1514 .hw.init = &(struct clk_init_data){
1533 .hw.init = &(struct clk_init_data){
1536 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_sel.hw },
1547 .hw.init = &(struct clk_init_data) {
1550 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_div.hw },
1562 .hw.init = &(struct clk_init_data){
1581 .hw.init = &(struct clk_init_data){
1584 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_sel.hw },
1595 .hw.init = &(struct clk_init_data) {
1598 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_div.hw },
1610 .hw.init = &(struct clk_init_data){
1618 &gxbb_vpu_0.hw,
1619 &gxbb_vpu_1.hw
1629 &gxbb_fclk_div4.hw,
1630 &gxbb_fclk_div3.hw,
1631 &gxbb_fclk_div5.hw,
1632 &gxbb_fclk_div7.hw,
1641 .hw.init = &(struct clk_init_data){
1660 .hw.init = &(struct clk_init_data){
1664 &gxbb_vapb_0_sel.hw
1676 .hw.init = &(struct clk_init_data) {
1680 &gxbb_vapb_0_div.hw
1693 .hw.init = &(struct clk_init_data){
1712 .hw.init = &(struct clk_init_data){
1716 &gxbb_vapb_1_sel.hw
1728 .hw.init = &(struct clk_init_data) {
1732 &gxbb_vapb_1_div.hw
1745 .hw.init = &(struct clk_init_data){
1753 &gxbb_vapb_0.hw,
1754 &gxbb_vapb_1.hw
1766 .hw.init = &(struct clk_init_data) {
1769 .parent_hws = (const struct clk_hw *[]) { &gxbb_vapb_sel.hw },
1790 .hw.init = &(struct clk_init_data) {
1810 { .hw = &gxbb_vid_pll_div.hw },
1827 .hw.init = &(struct clk_init_data){
1845 .hw.init = &(struct clk_init_data) {
1849 &gxbb_vid_pll_sel.hw
1857 &gxbb_vid_pll.hw,
1858 &gxbb_fclk_div4.hw,
1859 &gxbb_fclk_div3.hw,
1860 &gxbb_fclk_div5.hw,
1861 &gxbb_vid_pll.hw,
1862 &gxbb_fclk_div7.hw,
1863 &gxbb_mpll1.hw,
1872 .hw.init = &(struct clk_init_data){
1892 .hw.init = &(struct clk_init_data){
1911 .hw.init = &(struct clk_init_data) {
1914 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_sel.hw },
1925 .hw.init = &(struct clk_init_data) {
1928 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_sel.hw },
1940 .hw.init = &(struct clk_init_data){
1944 &gxbb_vclk_input.hw
1957 .hw.init = &(struct clk_init_data){
1961 &gxbb_vclk2_input.hw
1973 .hw.init = &(struct clk_init_data) {
1976 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_div.hw },
1987 .hw.init = &(struct clk_init_data) {
1990 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_div.hw },
2001 .hw.init = &(struct clk_init_data) {
2004 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
2015 .hw.init = &(struct clk_init_data) {
2018 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
2029 .hw.init = &(struct clk_init_data) {
2032 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
2043 .hw.init = &(struct clk_init_data) {
2046 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
2057 .hw.init = &(struct clk_init_data) {
2060 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
2071 .hw.init = &(struct clk_init_data) {
2074 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2085 .hw.init = &(struct clk_init_data) {
2088 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2099 .hw.init = &(struct clk_init_data) {
2102 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2113 .hw.init = &(struct clk_init_data) {
2116 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2127 .hw.init = &(struct clk_init_data) {
2130 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2139 .hw.init = &(struct clk_init_data){
2143 &gxbb_vclk_div2_en.hw
2152 .hw.init = &(struct clk_init_data){
2156 &gxbb_vclk_div4_en.hw
2165 .hw.init = &(struct clk_init_data){
2169 &gxbb_vclk_div6_en.hw
2178 .hw.init = &(struct clk_init_data){
2182 &gxbb_vclk_div12_en.hw
2191 .hw.init = &(struct clk_init_data){
2195 &gxbb_vclk2_div2_en.hw
2204 .hw.init = &(struct clk_init_data){
2208 &gxbb_vclk2_div4_en.hw
2217 .hw.init = &(struct clk_init_data){
2221 &gxbb_vclk2_div6_en.hw
2230 .hw.init = &(struct clk_init_data){
2234 &gxbb_vclk2_div12_en.hw
2242 &gxbb_vclk_div1.hw,
2243 &gxbb_vclk_div2.hw,
2244 &gxbb_vclk_div4.hw,
2245 &gxbb_vclk_div6.hw,
2246 &gxbb_vclk_div12.hw,
2247 &gxbb_vclk2_div1.hw,
2248 &gxbb_vclk2_div2.hw,
2249 &gxbb_vclk2_div4.hw,
2250 &gxbb_vclk2_div6.hw,
2251 &gxbb_vclk2_div12.hw,
2261 .hw.init = &(struct clk_init_data){
2277 .hw.init = &(struct clk_init_data){
2293 .hw.init = &(struct clk_init_data){
2305 &gxbb_vclk_div1.hw,
2306 &gxbb_vclk_div2.hw,
2307 &gxbb_vclk_div4.hw,
2308 &gxbb_vclk_div6.hw,
2309 &gxbb_vclk_div12.hw,
2310 &gxbb_vclk2_div1.hw,
2311 &gxbb_vclk2_div2.hw,
2312 &gxbb_vclk2_div4.hw,
2313 &gxbb_vclk2_div6.hw,
2314 &gxbb_vclk2_div12.hw,
2324 .hw.init = &(struct clk_init_data){
2344 .hw.init = &(struct clk_init_data) {
2348 &gxbb_cts_enci_sel.hw
2360 .hw.init = &(struct clk_init_data) {
2364 &gxbb_cts_encp_sel.hw
2376 .hw.init = &(struct clk_init_data) {
2380 &gxbb_cts_vdac_sel.hw
2392 .hw.init = &(struct clk_init_data) {
2396 &gxbb_hdmi_tx_sel.hw
2407 { .hw = &gxbb_fclk_div4.hw },
2408 { .hw = &gxbb_fclk_div3.hw },
2409 { .hw = &gxbb_fclk_div5.hw },
2419 .hw.init = &(struct clk_init_data){
2434 .hw.init = &(struct clk_init_data){
2437 .parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_sel.hw },
2448 .hw.init = &(struct clk_init_data) {
2451 .parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_div.hw },
2460 &gxbb_fclk_div4.hw,
2461 &gxbb_fclk_div3.hw,
2462 &gxbb_fclk_div5.hw,
2463 &gxbb_fclk_div7.hw,
2473 .hw.init = &(struct clk_init_data){
2489 .hw.init = &(struct clk_init_data){
2493 &gxbb_vdec_1_sel.hw
2505 .hw.init = &(struct clk_init_data) {
2509 &gxbb_vdec_1_div.hw
2523 .hw.init = &(struct clk_init_data){
2539 .hw.init = &(struct clk_init_data){
2543 &gxbb_vdec_hevc_sel.hw
2555 .hw.init = &(struct clk_init_data) {
2559 &gxbb_vdec_hevc_div.hw
2570 { .hw = &gxbb_vdec_1.hw },
2571 { .hw = &gxbb_vdec_hevc.hw },
2572 { .hw = &gxbb_mpll0.hw },
2573 { .hw = &gxbb_mpll1.hw },
2574 { .hw = &gxbb_mpll2.hw },
2575 { .hw = &gxbb_fclk_div4.hw },
2576 { .hw = &gxbb_fclk_div3.hw },
2577 { .hw = &gxbb_fclk_div5.hw },
2578 { .hw = &gxbb_fclk_div7.hw },
2579 { .hw = &gxbb_gp0_pll.hw },
2589 .hw.init = &(struct clk_init_data){
2609 .hw.init = &(struct clk_init_data){
2613 &gxbb_gen_clk_sel.hw
2625 .hw.init = &(struct clk_init_data){
2629 &gxbb_gen_clk_div.hw
2637 MESON_PCLK(_name, _reg, _bit, &gxbb_clk81.hw)
2722 static MESON_PCLK(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6, &gxbb_aiu.hw);
2723 static MESON_PCLK(gxbb_iec958, HHI_GCLK_MPEG1, 7, &gxbb_aiu_glue.hw);
2724 static MESON_PCLK(gxbb_i2s_out, HHI_GCLK_MPEG1, 8, &gxbb_aiu_glue.hw);
2725 static MESON_PCLK(gxbb_amclk, HHI_GCLK_MPEG1, 9, &gxbb_aiu_glue.hw);
2726 static MESON_PCLK(gxbb_aififo2, HHI_GCLK_MPEG1, 10, &gxbb_aiu_glue.hw);
2727 static MESON_PCLK(gxbb_mixer, HHI_GCLK_MPEG1, 11, &gxbb_aiu_glue.hw);
2728 static MESON_PCLK(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12, &gxbb_aiu_glue.hw);
2729 static MESON_PCLK(gxbb_adc, HHI_GCLK_MPEG1, 13, &gxbb_aiu_glue.hw);
2734 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
2735 [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw,
2736 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
2737 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
2738 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
2739 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,
2740 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
2741 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
2742 [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw,
2743 [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
2744 [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
2745 [CLKID_CLK81] = &gxbb_clk81.hw,
2746 [CLKID_MPLL0] = &gxbb_mpll0.hw,
2747 [CLKID_MPLL1] = &gxbb_mpll1.hw,
2748 [CLKID_MPLL2] = &gxbb_mpll2.hw,
2749 [CLKID_DDR] = &gxbb_ddr.hw,
2750 [CLKID_DOS] = &gxbb_dos.hw,
2751 [CLKID_ISA] = &gxbb_isa.hw,
2752 [CLKID_PL301] = &gxbb_pl301.hw,
2753 [CLKID_PERIPHS] = &gxbb_periphs.hw,
2754 [CLKID_SPICC] = &gxbb_spicc.hw,
2755 [CLKID_I2C] = &gxbb_i2c.hw,
2756 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw,
2757 [CLKID_SMART_CARD] = &gxbb_smart_card.hw,
2758 [CLKID_RNG0] = &gxbb_rng0.hw,
2759 [CLKID_UART0] = &gxbb_uart0.hw,
2760 [CLKID_SDHC] = &gxbb_sdhc.hw,
2761 [CLKID_STREAM] = &gxbb_stream.hw,
2762 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw,
2763 [CLKID_SDIO] = &gxbb_sdio.hw,
2764 [CLKID_ABUF] = &gxbb_abuf.hw,
2765 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw,
2766 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw,
2767 [CLKID_SPI] = &gxbb_spi.hw,
2768 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw,
2769 [CLKID_ETH] = &gxbb_eth.hw,
2770 [CLKID_DEMUX] = &gxbb_demux.hw,
2771 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw,
2772 [CLKID_IEC958] = &gxbb_iec958.hw,
2773 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw,
2774 [CLKID_AMCLK] = &gxbb_amclk.hw,
2775 [CLKID_AIFIFO2] = &gxbb_aififo2.hw,
2776 [CLKID_MIXER] = &gxbb_mixer.hw,
2777 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw,
2778 [CLKID_ADC] = &gxbb_adc.hw,
2779 [CLKID_BLKMV] = &gxbb_blkmv.hw,
2780 [CLKID_AIU] = &gxbb_aiu.hw,
2781 [CLKID_UART1] = &gxbb_uart1.hw,
2782 [CLKID_G2D] = &gxbb_g2d.hw,
2783 [CLKID_USB0] = &gxbb_usb0.hw,
2784 [CLKID_USB1] = &gxbb_usb1.hw,
2785 [CLKID_RESET] = &gxbb_reset.hw,
2786 [CLKID_NAND] = &gxbb_nand.hw,
2787 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw,
2788 [CLKID_USB] = &gxbb_usb.hw,
2789 [CLKID_VDIN1] = &gxbb_vdin1.hw,
2790 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw,
2791 [CLKID_EFUSE] = &gxbb_efuse.hw,
2792 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw,
2793 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw,
2794 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw,
2795 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw,
2796 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw,
2797 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw,
2798 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,
2799 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw,
2800 [CLKID_DVIN] = &gxbb_dvin.hw,
2801 [CLKID_UART2] = &gxbb_uart2.hw,
2802 [CLKID_SANA] = &gxbb_sana.hw,
2803 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw,
2804 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
2805 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw,
2806 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw,
2807 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw,
2808 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw,
2809 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw,
2810 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw,
2811 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw,
2812 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw,
2813 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw,
2814 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw,
2815 [CLKID_ENC480P] = &gxbb_enc480p.hw,
2816 [CLKID_RNG1] = &gxbb_rng1.hw,
2817 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw,
2818 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw,
2819 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw,
2820 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw,
2821 [CLKID_EDP] = &gxbb_edp.hw,
2822 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw,
2823 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw,
2824 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
2825 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
2826 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
2827 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
2828 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
2829 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
2830 [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
2831 [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
2832 [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
2833 [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw,
2834 [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw,
2835 [CLKID_MALI_0] = &gxbb_mali_0.hw,
2836 [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw,
2837 [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,
2838 [CLKID_MALI_1] = &gxbb_mali_1.hw,
2839 [CLKID_MALI] = &gxbb_mali.hw,
2840 [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
2841 [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
2842 [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
2843 [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,
2844 [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
2845 [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
2846 [CLKID_CTS_I958] = &gxbb_cts_i958.hw,
2847 [CLKID_32K_CLK] = &gxbb_32k_clk.hw,
2848 [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
2849 [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
2850 [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw,
2851 [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw,
2852 [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw,
2853 [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw,
2854 [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw,
2855 [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw,
2856 [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
2857 [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
2858 [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
2859 [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw,
2860 [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw,
2861 [CLKID_VPU_0] = &gxbb_vpu_0.hw,
2862 [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw,
2863 [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw,
2864 [CLKID_VPU_1] = &gxbb_vpu_1.hw,
2865 [CLKID_VPU] = &gxbb_vpu.hw,
2866 [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw,
2867 [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw,
2868 [CLKID_VAPB_0] = &gxbb_vapb_0.hw,
2869 [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw,
2870 [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw,
2871 [CLKID_VAPB_1] = &gxbb_vapb_1.hw,
2872 [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
2873 [CLKID_VAPB] = &gxbb_vapb.hw,
2874 [CLKID_HDMI_PLL_PRE_MULT] = &gxbb_hdmi_pll_pre_mult.hw,
2875 [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw,
2876 [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
2877 [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
2878 [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
2879 [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw,
2880 [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw,
2881 [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
2882 [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
2883 [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
2884 [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw,
2885 [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw,
2886 [CLKID_VDEC_1] = &gxbb_vdec_1.hw,
2887 [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw,
2888 [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw,
2889 [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw,
2890 [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw,
2891 [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw,
2892 [CLKID_GEN_CLK] = &gxbb_gen_clk.hw,
2893 [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw,
2894 [CLKID_HDMI_PLL_DCO] = &gxbb_hdmi_pll_dco.hw,
2895 [CLKID_HDMI_PLL_OD] = &gxbb_hdmi_pll_od.hw,
2896 [CLKID_HDMI_PLL_OD2] = &gxbb_hdmi_pll_od2.hw,
2897 [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw,
2898 [CLKID_GP0_PLL_DCO] = &gxbb_gp0_pll_dco.hw,
2899 [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw,
2900 [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw,
2901 [CLKID_VID_PLL] = &gxbb_vid_pll.hw,
2902 [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw,
2903 [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw,
2904 [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw,
2905 [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw,
2906 [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw,
2907 [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw,
2908 [CLKID_VCLK] = &gxbb_vclk.hw,
2909 [CLKID_VCLK2] = &gxbb_vclk2.hw,
2910 [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw,
2911 [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw,
2912 [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw,
2913 [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw,
2914 [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw,
2915 [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw,
2916 [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw,
2917 [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw,
2918 [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw,
2919 [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw,
2920 [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw,
2921 [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw,
2922 [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw,
2923 [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw,
2924 [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw,
2925 [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw,
2926 [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw,
2927 [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw,
2928 [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw,
2929 [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw,
2930 [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw,
2931 [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw,
2932 [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw,
2933 [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw,
2934 [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw,
2935 [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw,
2936 [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw,
2937 [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw,
2938 [CLKID_HDMI] = &gxbb_hdmi.hw,
2942 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
2943 [CLKID_HDMI_PLL] = &gxl_hdmi_pll.hw,
2944 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
2945 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
2946 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
2947 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,
2948 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
2949 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
2950 [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw,
2951 [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
2952 [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
2953 [CLKID_CLK81] = &gxbb_clk81.hw,
2954 [CLKID_MPLL0] = &gxbb_mpll0.hw,
2955 [CLKID_MPLL1] = &gxbb_mpll1.hw,
2956 [CLKID_MPLL2] = &gxbb_mpll2.hw,
2957 [CLKID_DDR] = &gxbb_ddr.hw,
2958 [CLKID_DOS] = &gxbb_dos.hw,
2959 [CLKID_ISA] = &gxbb_isa.hw,
2960 [CLKID_PL301] = &gxbb_pl301.hw,
2961 [CLKID_PERIPHS] = &gxbb_periphs.hw,
2962 [CLKID_SPICC] = &gxbb_spicc.hw,
2963 [CLKID_I2C] = &gxbb_i2c.hw,
2964 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw,
2965 [CLKID_SMART_CARD] = &gxbb_smart_card.hw,
2966 [CLKID_RNG0] = &gxbb_rng0.hw,
2967 [CLKID_UART0] = &gxbb_uart0.hw,
2968 [CLKID_SDHC] = &gxbb_sdhc.hw,
2969 [CLKID_STREAM] = &gxbb_stream.hw,
2970 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw,
2971 [CLKID_SDIO] = &gxbb_sdio.hw,
2972 [CLKID_ABUF] = &gxbb_abuf.hw,
2973 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw,
2974 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw,
2975 [CLKID_SPI] = &gxbb_spi.hw,
2976 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw,
2977 [CLKID_ETH] = &gxbb_eth.hw,
2978 [CLKID_DEMUX] = &gxbb_demux.hw,
2979 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw,
2980 [CLKID_IEC958] = &gxbb_iec958.hw,
2981 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw,
2982 [CLKID_AMCLK] = &gxbb_amclk.hw,
2983 [CLKID_AIFIFO2] = &gxbb_aififo2.hw,
2984 [CLKID_MIXER] = &gxbb_mixer.hw,
2985 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw,
2986 [CLKID_ADC] = &gxbb_adc.hw,
2987 [CLKID_BLKMV] = &gxbb_blkmv.hw,
2988 [CLKID_AIU] = &gxbb_aiu.hw,
2989 [CLKID_UART1] = &gxbb_uart1.hw,
2990 [CLKID_G2D] = &gxbb_g2d.hw,
2991 [CLKID_USB0] = &gxbb_usb0.hw,
2992 [CLKID_USB1] = &gxbb_usb1.hw,
2993 [CLKID_RESET] = &gxbb_reset.hw,
2994 [CLKID_NAND] = &gxbb_nand.hw,
2995 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw,
2996 [CLKID_USB] = &gxbb_usb.hw,
2997 [CLKID_VDIN1] = &gxbb_vdin1.hw,
2998 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw,
2999 [CLKID_EFUSE] = &gxbb_efuse.hw,
3000 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw,
3001 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw,
3002 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw,
3003 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw,
3004 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw,
3005 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw,
3006 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,
3007 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw,
3008 [CLKID_DVIN] = &gxbb_dvin.hw,
3009 [CLKID_UART2] = &gxbb_uart2.hw,
3010 [CLKID_SANA] = &gxbb_sana.hw,
3011 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw,
3012 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
3013 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw,
3014 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw,
3015 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw,
3016 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw,
3017 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw,
3018 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw,
3019 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw,
3020 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw,
3021 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw,
3022 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw,
3023 [CLKID_ENC480P] = &gxbb_enc480p.hw,
3024 [CLKID_RNG1] = &gxbb_rng1.hw,
3025 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw,
3026 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw,
3027 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw,
3028 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw,
3029 [CLKID_EDP] = &gxbb_edp.hw,
3030 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw,
3031 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw,
3032 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
3033 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
3034 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
3035 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
3036 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
3037 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
3038 [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
3039 [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
3040 [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
3041 [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw,
3042 [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw,
3043 [CLKID_MALI_0] = &gxbb_mali_0.hw,
3044 [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw,
3045 [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,
3046 [CLKID_MALI_1] = &gxbb_mali_1.hw,
3047 [CLKID_MALI] = &gxbb_mali.hw,
3048 [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
3049 [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
3050 [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
3051 [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,
3052 [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
3053 [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
3054 [CLKID_CTS_I958] = &gxbb_cts_i958.hw,
3055 [CLKID_32K_CLK] = &gxbb_32k_clk.hw,
3056 [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
3057 [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
3058 [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw,
3059 [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw,
3060 [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw,
3061 [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw,
3062 [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw,
3063 [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw,
3064 [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
3065 [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
3066 [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
3067 [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw,
3068 [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw,
3069 [CLKID_VPU_0] = &gxbb_vpu_0.hw,
3070 [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw,
3071 [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw,
3072 [CLKID_VPU_1] = &gxbb_vpu_1.hw,
3073 [CLKID_VPU] = &gxbb_vpu.hw,
3074 [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw,
3075 [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw,
3076 [CLKID_VAPB_0] = &gxbb_vapb_0.hw,
3077 [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw,
3078 [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw,
3079 [CLKID_VAPB_1] = &gxbb_vapb_1.hw,
3080 [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
3081 [CLKID_VAPB] = &gxbb_vapb.hw,
3082 [CLKID_MPLL0_DIV] = &gxl_mpll0_div.hw,
3083 [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
3084 [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
3085 [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
3086 [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw,
3087 [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw,
3088 [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
3089 [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
3090 [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
3091 [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw,
3092 [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw,
3093 [CLKID_VDEC_1] = &gxbb_vdec_1.hw,
3094 [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw,
3095 [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw,
3096 [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw,
3097 [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw,
3098 [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw,
3099 [CLKID_GEN_CLK] = &gxbb_gen_clk.hw,
3100 [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw,
3101 [CLKID_HDMI_PLL_DCO] = &gxl_hdmi_pll_dco.hw,
3102 [CLKID_HDMI_PLL_OD] = &gxl_hdmi_pll_od.hw,
3103 [CLKID_HDMI_PLL_OD2] = &gxl_hdmi_pll_od2.hw,
3104 [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw,
3105 [CLKID_GP0_PLL_DCO] = &gxl_gp0_pll_dco.hw,
3106 [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw,
3107 [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw,
3108 [CLKID_VID_PLL] = &gxbb_vid_pll.hw,
3109 [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw,
3110 [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw,
3111 [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw,
3112 [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw,
3113 [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw,
3114 [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw,
3115 [CLKID_VCLK] = &gxbb_vclk.hw,
3116 [CLKID_VCLK2] = &gxbb_vclk2.hw,
3117 [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw,
3118 [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw,
3119 [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw,
3120 [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw,
3121 [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw,
3122 [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw,
3123 [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw,
3124 [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw,
3125 [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw,
3126 [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw,
3127 [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw,
3128 [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw,
3129 [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw,
3130 [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw,
3131 [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw,
3132 [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw,
3133 [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw,
3134 [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw,
3135 [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw,
3136 [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw,
3137 [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw,
3138 [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw,
3139 [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw,
3140 [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw,
3141 [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw,
3142 [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw,
3143 [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw,
3144 [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw,
3145 [CLKID_HDMI] = &gxbb_hdmi.hw,
3146 [CLKID_ACODEC] = &gxl_acodec.hw,