clk/mediatek/clk-fhctl.c

59 		readl(regs->reg_hp_en), readl(regs->reg_clk_con),
60 		readl(regs->reg_slope0), readl(regs->reg_slope1));
62 		readl(regs->reg_cfg), readl(regs->reg_updnlmt),
63 		readl(regs->reg_dds), readl(regs->reg_dvfs),
64 		readl(regs->reg_mon));
65 	pr_info("pcw<%x>\n", readl(pll->pcw_addr));
73 	writel((readl(regs->reg_cfg) & ~(data->frddsx_en)), regs->reg_cfg);
74 	writel((readl(regs->reg_cfg) & ~(data->sfstrx_en)), regs->reg_cfg);
75 	writel((readl(regs->reg_cfg) & ~(data->fhctlx_en)), regs->reg_cfg);
79 		r = readl(regs->reg_cfg);
84 		r = readl(regs->reg_cfg);
89 		writel((readl(pll->pcw_addr) & data->dds_mask) | data->tgl_org,
93 		updnlmt_val = PERCENT_TO_DDSLMT((readl(regs->reg_dds) &
98 		writel(readl(regs->reg_hp_en) | BIT(data->fh_id),
101 		writel(readl(regs->reg_cfg) | data->frddsx_en, regs->reg_cfg);
103 		writel(readl(regs->reg_cfg) | data->fhctlx_en, regs->reg_cfg);
107 		writel(readl(regs->reg_hp_en) & ~BIT(data->fh_id),
128 	writel((readl(pll->pcw_addr) & dds_mask) | data->tgl_org,
131 	writel(readl(regs->reg_cfg) | data->sfstrx_en, regs->reg_cfg);
132 	writel(readl(regs->reg_cfg) | data->fhctlx_en, regs->reg_cfg);
136 	writel(readl(regs->reg_hp_en) | BIT(data->fh_id), regs->reg_hp_en);
148 	con_pcw_tmp = readl(pll->pcw_addr) & (~dds_mask);
149 	con_pcw_tmp = (con_pcw_tmp | (readl(regs->reg_mon) & dds_mask) |
153 	writel(readl(regs->reg_hp_en) & ~BIT(data->fh_id), regs->reg_hp_en);
165 	regval = readl(pll->pd_addr) >> pll->data->pd_shift;
175 	regval = readl(pll->pd_addr);
249 	val = readl(regs.reg_clk_con) | BIT(data.fh_id);
252 	val = readl(regs.reg_rst_con) & ~BIT(data.fh_id);
254 	val = readl(regs.reg_rst_con) | BIT(data.fh_id);