clk/ingenic/cgu.c

88 	u32 ctl;
93 	ctl = readl(cgu->base + pll_info->reg);
95 	m = (ctl >> pll_info->m_shift) & GENMASK(pll_info->m_bits - 1, 0);
97 	n = (ctl >> pll_info->n_shift) & GENMASK(pll_info->n_bits - 1, 0);
101 		od_enc = ctl >> pll_info->od_shift;
106 		ctl = readl(cgu->base + pll_info->bypass_reg);
108 		bypass = !!(ctl & BIT(pll_info->bypass_bit));
190 	u32 ctl;
195 	return readl_poll_timeout(cgu->base + pll_info->reg, ctl,
196 				  ctl & BIT(pll_info->stable_bit),
211 	u32 ctl;
220 	ctl = readl(cgu->base + pll_info->reg);
222 	ctl &= ~(GENMASK(pll_info->m_bits - 1, 0) << pll_info->m_shift);
223 	ctl |= (m - pll_info->m_offset) << pll_info->m_shift;
225 	ctl &= ~(GENMASK(pll_info->n_bits - 1, 0) << pll_info->n_shift);
226 	ctl |= (n - pll_info->n_offset) << pll_info->n_shift;
229 		ctl &= ~(GENMASK(pll_info->od_bits - 1, 0) << pll_info->od_shift);
230 		ctl |= pll_info->od_encoding[od - 1] << pll_info->od_shift;
233 	writel(ctl, cgu->base + pll_info->reg);
239 	if (pll_info->enable_bit >= 0 && (ctl & BIT(pll_info->enable_bit)))
255 	u32 ctl;
262 		ctl = readl(cgu->base + pll_info->bypass_reg);
264 		ctl &= ~BIT(pll_info->bypass_bit);
266 		writel(ctl, cgu->base + pll_info->bypass_reg);
269 	ctl = readl(cgu->base + pll_info->reg);
271 	ctl |= BIT(pll_info->enable_bit);
273 	writel(ctl, cgu->base + pll_info->reg);
288 	u32 ctl;
294 	ctl = readl(cgu->base + pll_info->reg);
296 	ctl &= ~BIT(pll_info->enable_bit);
298 	writel(ctl, cgu->base + pll_info->reg);
308 	u32 ctl;
313 	ctl = readl(cgu->base + pll_info->reg);
315 	return !!(ctl & BIT(pll_info->enable_bit));