clk/imx/clk.h

95 struct clk_hw *imx_clk_fracn_gppll(const char *name, const char *parent_name, void __iomem *base,
97 struct clk_hw *imx_clk_fracn_gppll_integer(const char *name, const char *parent_name,
104 #define imx_clk_cpu(name, parent_name, div, mux, pll, step) \
105 	to_clk(imx_clk_hw_cpu(name, parent_name, div, mux, pll, step))
107 #define clk_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
109 	to_clk(clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
112 #define imx_clk_pllv3(type, name, parent_name, base, div_mask) \
113 	to_clk(imx_clk_hw_pllv3(type, name, parent_name, base, div_mask))
115 #define imx_clk_pfd(name, parent_name, reg, idx) \
116 	to_clk(imx_clk_hw_pfd(name, parent_name, reg, idx))
118 #define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) \
119 	to_clk(imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask))
121 #define imx_clk_fixed(name, rate) \
122 	to_clk(imx_clk_hw_fixed(name, rate))
124 #define imx_clk_fixed_factor(name, parent, mult, div) \
125 	to_clk(imx_clk_hw_fixed_factor(name, parent, mult, div))
127 #define imx_clk_divider(name, parent, reg, shift, width) \
128 	to_clk(imx_clk_hw_divider(name, parent, reg, shift, width))
130 #define imx_clk_divider_flags(name, parent, reg, shift, width, flags) \
131 	to_clk(imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags))
133 #define imx_clk_gate(name, parent, reg, shift) \
134 	to_clk(imx_clk_hw_gate(name, parent, reg, shift))
136 #define imx_clk_gate_dis(name, parent, reg, shift) \
137 	to_clk(imx_clk_hw_gate_dis(name, parent, reg, shift))
139 #define imx_clk_gate2(name, parent, reg, shift) \
140 	to_clk(imx_clk_hw_gate2(name, parent, reg, shift))
142 #define imx_clk_gate2_cgr(name, parent, reg, shift, cgr_val) \
143 	to_clk(__imx_clk_hw_gate2(name, parent, reg, shift, cgr_val, 0, NULL))
145 #define imx_clk_gate2_flags(name, parent, reg, shift, flags) \
146 	to_clk(imx_clk_hw_gate2_flags(name, parent, reg, shift, flags))
148 #define imx_clk_mux(name, reg, shift, width, parents, num_parents) \
149 	to_clk(imx_clk_hw_mux(name, reg, shift, width, parents, num_parents))
151 #define imx_clk_mux_flags(name, reg, shift, width, parents, num_parents, flags) \
152 	to_clk(imx_clk_hw_mux_flags(name, reg, shift, width, parents, num_parents, flags))
154 #define imx_clk_mux2_flags(name, reg, shift, width, parents, num_parents, flags) \
155 	to_clk(imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, flags))
157 #define imx_clk_pllv1(type, name, parent, base) \
158 	to_clk(imx_clk_hw_pllv1(type, name, parent, base))
160 #define imx_clk_pllv2(name, parent, base) \
161 	to_clk(imx_clk_hw_pllv2(name, parent, base))
163 #define imx_clk_hw_gate(name, parent, reg, shift) \
164 	imx_clk_hw_gate_flags(name, parent, reg, shift, 0)
166 #define imx_clk_hw_gate2(name, parent, reg, shift) \
167 	imx_clk_hw_gate2_flags(name, parent, reg, shift, 0)
169 #define imx_clk_hw_gate_dis(name, parent, reg, shift) \
170 	imx_clk_hw_gate_dis_flags(name, parent, reg, shift, 0)
172 #define imx_clk_hw_gate_dis_flags(name, parent, reg, shift, flags) \
173 	__imx_clk_hw_gate(name, parent, reg, shift, flags, CLK_GATE_SET_TO_DISABLE)
175 #define imx_clk_hw_gate_flags(name, parent, reg, shift, flags) \
176 	__imx_clk_hw_gate(name, parent, reg, shift, flags, 0)
178 #define imx_clk_hw_gate2_flags(name, parent, reg, shift, flags) \
179 	__imx_clk_hw_gate2(name, parent, reg, shift, 0x3, flags, NULL)
181 #define imx_clk_hw_gate2_shared(name, parent, reg, shift, shared_count) \
182 	__imx_clk_hw_gate2(name, parent, reg, shift, 0x3, 0, shared_count)
184 #define imx_clk_hw_gate2_shared2(name, parent, reg, shift, shared_count) \
185 	__imx_clk_hw_gate2(name, parent, reg, shift, 0x3, CLK_OPS_PARENT_ENABLE, shared_count)
187 #define imx_clk_hw_gate3(name, parent, reg, shift) \
188 	imx_clk_hw_gate3_flags(name, parent, reg, shift, 0)
190 #define imx_clk_hw_gate3_flags(name, parent, reg, shift, flags) \
191 	__imx_clk_hw_gate(name, parent, reg, shift, flags | CLK_OPS_PARENT_ENABLE, 0)
193 #define imx_clk_hw_gate4(name, parent, reg, shift) \
194 	imx_clk_hw_gate4_flags(name, parent, reg, shift, 0)
196 #define imx_clk_hw_gate4_flags(name, parent, reg, shift, flags) \
197 	imx_clk_hw_gate2_flags(name, parent, reg, shift, flags | CLK_OPS_PARENT_ENABLE)
199 #define imx_clk_hw_mux2(name, reg, shift, width, parents, num_parents) \
200 	imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, 0)
202 #define imx_clk_hw_mux(name, reg, shift, width, parents, num_parents) \
203 	__imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, 0, 0)
205 #define imx_clk_hw_mux_flags(name, reg, shift, width, parents, num_parents, flags) \
206 	__imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, flags, 0)
208 #define imx_clk_hw_mux_ldb(name, reg, shift, width, parents, num_parents) \
209 	__imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, CLK_SET_RATE_PARENT, CLK_MUX_READ_ONLY)
211 #define imx_clk_hw_mux2_flags(name, reg, shift, width, parents, num_parents, flags) \
212 	__imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, flags | CLK_OPS_PARENT_ENABLE, 0)
214 #define imx_clk_hw_divider(name, parent, reg, shift, width) \
215 	__imx_clk_hw_divider(name, parent, reg, shift, width, CLK_SET_RATE_PARENT)
217 #define imx_clk_hw_divider2(name, parent, reg, shift, width) \
218 	__imx_clk_hw_divider(name, parent, reg, shift, width, \
221 #define imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags) \
222 	__imx_clk_hw_divider(name, parent, reg, shift, width, flags)
224 #define imx_clk_hw_pll14xx(name, parent_name, base, pll_clk) \
225 	imx_dev_clk_hw_pll14xx(NULL, name, parent_name, base, pll_clk)
227 struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name,
231 struct clk_hw *imx_clk_hw_pllv1(enum imx_pllv1_type type, const char *name,
234 struct clk_hw *imx_clk_hw_pllv2(const char *name, const char *parent,
237 struct clk_hw *imx_clk_hw_frac_pll(const char *name, const char *parent_name,
240 struct clk_hw *imx_clk_hw_sscg_pll(const char *name,
260 struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name,
280 struct clk_hw *imx_clk_hw_pllv4(enum imx_pllv4_type type, const char *name,
283 struct clk_hw *clk_hw_register_gate2(struct device *dev, const char *name,
290 			const char *name, unsigned long rate);
293 			const char *name, unsigned long rate);
296 					 const char *name, unsigned long rate);
298 struct clk_hw *imx_get_clk_hw_by_name(struct device_node *np, const char *name);
300 struct clk_hw *imx_clk_hw_gate_exclusive(const char *name, const char *parent,
303 struct clk_hw *imx_clk_hw_pfd(const char *name, const char *parent_name,
306 struct clk_hw *imx_clk_hw_pfdv2(enum imx_pfdv2_type type, const char *name,
309 struct clk_hw *imx_clk_hw_busy_divider(const char *name, const char *parent_name,
313 struct clk_hw *imx_clk_hw_busy_mux(const char *name, void __iomem *reg, u8 shift,
317 struct clk_hw *imx7ulp_clk_hw_composite(const char *name,
323 struct clk_hw *imx8ulp_clk_hw_composite(const char *name,
329 struct clk_hw *imx_clk_hw_fixup_divider(const char *name, const char *parent,
333 struct clk_hw *imx_clk_hw_fixup_mux(const char *name, void __iomem *reg,
344 static inline struct clk_hw *imx_clk_hw_fixed(const char *name, int rate)
346 	return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate);
349 static inline struct clk_hw *imx_clk_hw_fixed_factor(const char *name,
352 	return clk_hw_register_fixed_factor(NULL, name, parent,
356 static inline struct clk_hw *imx_clk_hw_divider_closest(const char *name,
361 	return clk_hw_register_divider(NULL, name, parent, 0,
365 static inline struct clk_hw *__imx_clk_hw_divider(const char *name,
370 	return clk_hw_register_divider(NULL, name, parent, flags,
374 static inline struct clk_hw *__imx_clk_hw_gate(const char *name, const char *parent,
379 	return clk_hw_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
383 static inline struct clk_hw *__imx_clk_hw_gate2(const char *name, const char *parent,
388 	return clk_hw_register_gate2(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
392 static inline struct clk_hw *__imx_clk_hw_mux(const char *name, void __iomem *reg,
396 	return clk_hw_register_mux(NULL, name, parents, num_parents,
401 struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name,
418 struct clk_hw *__imx8m_clk_hw_composite(const char *name,
425 #define _imx8m_clk_hw_composite(name, parent_names, reg, composite_flags, flags) \
426 	__imx8m_clk_hw_composite(name, parent_names, \
429 #define imx8m_clk_hw_composite(name, parent_names, reg) \
430 	_imx8m_clk_hw_composite(name, parent_names, reg, \
433 #define imx8m_clk_hw_composite_flags(name, parent_names, reg, flags) \
434 	_imx8m_clk_hw_composite(name, parent_names, reg, \
437 #define imx8m_clk_hw_composite_critical(name, parent_names, reg) \
438 	_imx8m_clk_hw_composite(name, parent_names, reg, \
441 #define imx8m_clk_hw_composite_bus(name, parent_names, reg)	\
442 	_imx8m_clk_hw_composite(name, parent_names, reg, \
445 #define imx8m_clk_hw_composite_bus_critical(name, parent_names, reg)	\
446 	_imx8m_clk_hw_composite(name, parent_names, reg, \
449 #define imx8m_clk_hw_composite_core(name, parent_names, reg)	\
450 	_imx8m_clk_hw_composite(name, parent_names, reg, \
453 #define imx8m_clk_hw_fw_managed_composite(name, parent_names, reg) \
454 	_imx8m_clk_hw_composite(name, parent_names, reg, \
458 #define imx8m_clk_hw_fw_managed_composite_critical(name, parent_names, reg) \
459 	_imx8m_clk_hw_composite(name, parent_names, reg, \
463 struct clk_hw *imx93_clk_composite_flags(const char *name,
469 #define imx93_clk_composite(name, parent_names, num_parents, reg, domain_id) \
470 	imx93_clk_composite_flags(name, parent_names, num_parents, reg, domain_id \
473 struct clk_hw *imx93_clk_gate(struct device *dev, const char *name, const char *parent_name,
477 struct clk_hw *imx_clk_hw_divider_gate(const char *name, const char *parent_name,
482 struct clk_hw *imx_clk_gpr_mux(const char *name, const char *compatible,