clk/imx/clk-sscg-pll.c

73 	int divr2, divf2;
136 		do_div(temp_setup->vco2, temp_setup->divr2 + 1);
175 	for (temp_setup->divr2 = 0; temp_setup->divr2 <= PLL_DIVR2_MAX;
176 	     temp_setup->divr2++) {
178 		do_div(temp_setup->ref_div2, temp_setup->divr2 + 1);
331 	u32 val, divr1, divf1, divr2, divf2, divq;
336 	divr2 = FIELD_GET(PLL_DIVR2_MASK, val);
348 		do_div(temp64, (divr2 + 1) * (divq + 1));
352 		do_div(temp64, (divr1 + 1) * (divr2 + 1) * (divq + 1));
377 	val |= FIELD_PREP(PLL_DIVR2_MASK, setup->divr2);