clk/imx/clk-sscg-pll.c

73 	int divr2, divf2;
138 		temp_setup->vco2 *= temp_setup->divf2 + 1;
160 	for (temp_setup->divf2 = 0; temp_setup->divf2 <= PLL_DIVF2_MAX;
161 	     temp_setup->divf2++) {
331 	u32 val, divr1, divf1, divr2, divf2, divq;
338 	divf2 = FIELD_GET(PLL_DIVF2_MASK, val);
347 		temp64 *= divf2;
351 		temp64 *= (divf1 + 1) * (divf2 + 1);
375 	val |= FIELD_PREP(PLL_DIVF2_MASK, setup->divf2);