clk/imx/clk-pllv4.c

60 static inline int clk_pllv4_wait_lock(struct clk_pllv4 *pll)
64 	return readl_poll_timeout(pll->base  + PLL_CSR_OFFSET,
70 	struct clk_pllv4 *pll = to_clk_pllv4(hw);
72 	if (readl_relaxed(pll->base) & PLL_EN)
81 	struct clk_pllv4 *pll = to_clk_pllv4(hw);
85 	mult = readl_relaxed(pll->base + pll->cfg_offset);
89 	mfn = readl_relaxed(pll->base + pll->num_offset);
90 	mfd = readl_relaxed(pll->base + pll->denom_offset);
101 	struct clk_pllv4 *pll = to_clk_pllv4(hw);
109 	if (pll->use_mult_range) {
158 static bool clk_pllv4_is_valid_mult(struct clk_pllv4 *pll, unsigned int mult)
163 	if (pll->use_mult_range) {
180 	struct clk_pllv4 *pll = to_clk_pllv4(hw);
186 	if (!clk_pllv4_is_valid_mult(pll, mult))
197 	val = readl_relaxed(pll->base + pll->cfg_offset);
200 	writel_relaxed(val, pll->base + pll->cfg_offset);
202 	writel_relaxed(mfn, pll->base + pll->num_offset);
203 	writel_relaxed(mfd, pll->base + pll->denom_offset);
211 	struct clk_pllv4 *pll = to_clk_pllv4(hw);
213 	val = readl_relaxed(pll->base);
215 	writel_relaxed(val, pll->base);
217 	return clk_pllv4_wait_lock(pll);
223 	struct clk_pllv4 *pll = to_clk_pllv4(hw);
225 	val = readl_relaxed(pll->base);
227 	writel_relaxed(val, pll->base);
242 	struct clk_pllv4 *pll;
247 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
248 	if (!pll)
251 	pll->base = base;
255 		pll->cfg_offset = IMX8ULP_PLL_CFG_OFFSET;
256 		pll->num_offset = IMX8ULP_PLL_NUM_OFFSET;
257 		pll->denom_offset = IMX8ULP_PLL_DENOM_OFFSET;
259 			pll->use_mult_range = true;
261 		pll->cfg_offset = PLL_CFG_OFFSET;
262 		pll->num_offset = PLL_NUM_OFFSET;
263 		pll->denom_offset = PLL_DENOM_OFFSET;
272 	pll->hw.init = &init;
274 	hw = &pll->hw;
277 		kfree(pll);