clk/imx/clk-pllv3.c

36  * @power_bit:	 pll power bit mask
61 static int clk_pllv3_wait_lock(struct clk_pllv3 *pll)
63 	u32 val = readl_relaxed(pll->base) & pll->power_bit;
65 	/* No need to wait for lock when pll is not powered up */
66 	if ((pll->powerup_set && !val) || (!pll->powerup_set && val))
69 	return readl_relaxed_poll_timeout(pll->base, val, val & BM_PLL_LOCK,
75 	struct clk_pllv3 *pll = to_clk_pllv3(hw);
78 	val = readl_relaxed(pll->base);
79 	if (pll->powerup_set)
80 		val |= pll->power_bit;
82 		val &= ~pll->power_bit;
83 	writel_relaxed(val, pll->base);
85 	return clk_pllv3_wait_lock(pll);
90 	struct clk_pllv3 *pll = to_clk_pllv3(hw);
93 	val = readl_relaxed(pll->base);
94 	if (pll->powerup_set)
95 		val &= ~pll->power_bit;
97 		val |= pll->power_bit;
98 	writel_relaxed(val, pll->base);
103 	struct clk_pllv3 *pll = to_clk_pllv3(hw);
105 	if (readl_relaxed(pll->base) & BM_PLL_LOCK)
114 	struct clk_pllv3 *pll = to_clk_pllv3(hw);
115 	u32 div = (readl_relaxed(pll->base) >> pll->div_shift)  & pll->div_mask;
132 	struct clk_pllv3 *pll = to_clk_pllv3(hw);
142 	val = readl_relaxed(pll->base);
143 	val &= ~(pll->div_mask << pll->div_shift);
144 	val |= (div << pll->div_shift);
145 	writel_relaxed(val, pll->base);
147 	return clk_pllv3_wait_lock(pll);
162 	struct clk_pllv3 *pll = to_clk_pllv3(hw);
163 	u32 div = readl_relaxed(pll->base) & pll->div_mask;
188 	struct clk_pllv3 *pll = to_clk_pllv3(hw);
197 	val = readl_relaxed(pll->base);
198 	val &= ~pll->div_mask;
200 	writel_relaxed(val, pll->base);
202 	return clk_pllv3_wait_lock(pll);
217 	struct clk_pllv3 *pll = to_clk_pllv3(hw);
218 	u32 mfn = readl_relaxed(pll->base + pll->num_offset);
219 	u32 mfd = readl_relaxed(pll->base + pll->denom_offset);
220 	u32 div = readl_relaxed(pll->base) & pll->div_mask;
264 	struct clk_pllv3 *pll = to_clk_pllv3(hw);
284 	val = readl_relaxed(pll->base);
285 	val &= ~pll->div_mask;
287 	writel_relaxed(val, pll->base);
288 	writel_relaxed(mfn, pll->base + pll->num_offset);
289 	writel_relaxed(mfd, pll->base + pll->denom_offset);
291 	return clk_pllv3_wait_lock(pll);
348 	struct clk_pllv3 *pll = to_clk_pllv3(hw);
351 	mf.mfn = readl_relaxed(pll->base + pll->num_offset);
352 	mf.mfd = readl_relaxed(pll->base + pll->denom_offset);
353 	mf.mfi = (readl_relaxed(pll->base) & pll->div_mask) ? 22 : 20;
369 	struct clk_pllv3 *pll = to_clk_pllv3(hw);
374 	val = readl_relaxed(pll->base);
376 		val &= ~pll->div_mask;	/* clear bit for mfi=20 */
378 		val |= pll->div_mask;	/* set bit for mfi=22 */
379 	writel_relaxed(val, pll->base);
381 	writel_relaxed(mf.mfn, pll->base + pll->num_offset);
382 	writel_relaxed(mf.mfd, pll->base + pll->denom_offset);
384 	return clk_pllv3_wait_lock(pll);
399 	struct clk_pllv3 *pll = to_clk_pllv3(hw);
401 	return pll->ref_clock;
415 	struct clk_pllv3 *pll;
421 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
422 	if (!pll)
425 	pll->power_bit = BM_PLL_POWER;
426 	pll->num_offset = PLL_NUM_OFFSET;
427 	pll->denom_offset = PLL_DENOM_OFFSET;
435 		pll->num_offset = PLL_VF610_NUM_OFFSET;
436 		pll->denom_offset = PLL_VF610_DENOM_OFFSET;
439 		pll->div_shift = 1;
443 		pll->powerup_set = true;
446 		pll->num_offset = PLL_IMX7_NUM_OFFSET;
447 		pll->denom_offset = PLL_IMX7_DENOM_OFFSET;
453 		pll->power_bit = IMX7_ENET_PLL_POWER;
454 		pll->ref_clock = 1000000000;
458 		pll->ref_clock = 500000000;
462 		pll->power_bit = IMX7_DDR_PLL_POWER;
463 		pll->num_offset = PLL_IMX7_NUM_OFFSET;
464 		pll->denom_offset = PLL_IMX7_DENOM_OFFSET;
470 	pll->base = base;
471 	pll->div_mask = div_mask;
479 	pll->hw.init = &init;
480 	hw = &pll->hw;
484 		kfree(pll);