clk/imx/clk-imx8ulp.c

84 	struct pcc_reset_dev *pcc_reset = to_pcc_reset_dev(rcdev);
85 	u32 offset = pcc_reset->resets[id];
89 	spin_lock_irqsave(pcc_reset->lock, flags);
91 	val = readl(pcc_reset->base + offset);
93 	writel(val, pcc_reset->base + offset);
95 	spin_unlock_irqrestore(pcc_reset->lock, flags);
102 	struct pcc_reset_dev *pcc_reset = to_pcc_reset_dev(rcdev);
103 	u32 offset = pcc_reset->resets[id];
107 	spin_lock_irqsave(pcc_reset->lock, flags);
109 	val = readl(pcc_reset->base + offset);
111 	writel(val, pcc_reset->base + offset);
113 	spin_unlock_irqrestore(pcc_reset->lock, flags);
128 	struct pcc_reset_dev *pcc_reset;
130 	pcc_reset = devm_kzalloc(dev, sizeof(*pcc_reset), GFP_KERNEL);
131 	if (!pcc_reset)
134 	pcc_reset->base = base;
135 	pcc_reset->lock = &imx_ccm_lock;
136 	pcc_reset->resets = resets;
137 	pcc_reset->rcdev.owner = THIS_MODULE;
138 	pcc_reset->rcdev.nr_resets = nr_resets;
139 	pcc_reset->rcdev.ops = &imx8ulp_pcc_reset_ops;
140 	pcc_reset->rcdev.of_node = np;
142 	return devm_reset_controller_register(dev, &pcc_reset->rcdev);